Abstract: Disclosed is a method and apparatus for power-efficiently processing sensor data. In one embodiment, the operations implemented include: configuring a sensor fusion engine and a peripheral controller with a general purpose processor; placing the general purpose processor into a low-power sleep mode; reading data from a sensor and storing the data into a companion memory with the peripheral controller; processing the data in the companion memory with the sensor fusion engine; and awaking the general purpose processor from the low-power sleep mode.

Abstract: Disclosed is an apparatus and method for power efficient processor scheduling of features. In one embodiment, features may be scheduled for sequential computing, and each scheduled feature may receive a sensor data sample as input. In one embodiment, scheduling may be based at least in part on each respective feature's estimated power usage. In one embodiment, a first feature in the sequential schedule of features may be computed and before computing a second feature in the sequential schedule of features, a termination condition may be evaluated.

Abstract: Systems, methods, and computer programs are disclosed for reducing motion-to-photon latency and memory bandwidth in a virtual reality display system. An exemplary method involves receiving sensor data from one or more sensors tracking translational and rotational motion of a user for a virtual reality application. An updated position of the user is computed based on the received sensor data. The speed and acceleration of the user movement may be computed based on the sensor data. The updated position, the speed, and the acceleration may be provided to a warp engine configured to update a rendered image before sending to a virtual reality display based on one or more of the updated position, the speed, and the acceleration.

Abstract: Disclosed are methods and apparatus for transmitting sensor timing correction messages with a host controller. The methods and apparatus determine synchronization messages that are transmitted to a sensor coupled with the host controller via an interface, where the messages indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor. Additionally, a delay time message is determined that indicates a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message. The synchronization message is transmitted with the delay time message in an information message to the sensor, where information message is configured to allow the sensor to correct timing of a sensor timer by accounting for the delay time.

Abstract: Disclosed are methods and apparatus for synchronizing a controller and sensors in a system. A timestamp is provided in a host controller of an interface event on an interface coupled with host controller through detecting a message from a sensor on the interface that identifies the issuance of the interface event caused by the sensor at a first time. In response, the controller issues first and second events on the interface at respective second and third times, while concurrently counting cycles of a clock in the controller after each issuance. The controller also receives a first and second sensor counts representing the internal sensor clock times noted for the first and second events. The controller may then accurately calculate the timestamp of the interface event corresponding to the first time based on both internal controller counts and the sensor counts without needing a timestamp from the sensor directly.

Abstract: Disclosed aspects relate to methods and apparatus for correcting a first sensor clock of a first sensor. The disclosed methods and apparatus effectuate receiving first and seconds signals in a sensor from a processor at known different times related to the timing of the processor clock. Based on the measured time interval between the times of the first and second signals as determined by the sensor, a clock correction factor may be determined in the sensor for correcting the timing of the sensor clock to be synchronized with the processor clock.

Abstract: Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.

Abstract: Systems and methods for external access detection and recovery in a subsystem of a system-on-a-chip (SoC) in a portable computing device (PCD) are presented. In operation, a subsystem of the SoC is operated in an internal mode independently of the SoC while the SoC is in a low power state, such as a non-functional or zero power state or mode. The subsystem comprises a processor in communication with a memory, a sensor, and a monitor module. The monitor module detects when the processor of the subsystem requests access to a component external to the subsystem. In response to this detected request, the SoC is caused to enter into a full power state or mode, and the subsystem is caused to exit the internal mode of operation.

Abstract: A user equipment (UE) controls power consumption of the UE based on mobility information and channel conditions experienced by the UE. In one instance, the UE determines its level of mobility based on a Doppler frequency spread of received communications. The UE disables a motion sensor when the level of mobility is above a first threshold. The UE then controls the communications based on the motion sensor and channel conditions experienced by the UE when the level of mobility is below the first threshold.

Abstract: Disclosed is a method and apparatus for power-efficiently processing sensor data. In one embodiment, the operations implemented include: configuring a sensor fusion engine and a peripheral controller with a general purpose processor; placing the general purpose processor into a low-power sleep mode; reading data from a sensor and storing the data into a companion memory with the peripheral controller; processing the data in the companion memory with the sensor fusion engine; and awaking the general purpose processor from the low-power sleep mode.

Abstract: Systems and methods for external access detection and recovery in a subsystem of a system-on-a-chip (SoC) in a portable computing device (PCD) are presented. In operation, a subsystem of the SoC is operated in an internal mode independently of the SoC while the SoC is in a low power state, such as a non-functional or zero power state or mode. The subsystem comprises a processor in communication with a memory, a sensor, and a monitor module. The monitor module detects when the processor of the subsystem requests access to a component external to the subsystem. In response to this detected request, the SoC is caused to enter into a full power state or mode, and the subsystem is caused to exit the internal mode of operation.

Abstract: A dynamic bypass capacitance is provided for a power rail. The dynamic bypass capacitance equals a first bypass capacitance during an idle mode for a digital core powered by the power rail. During an active mode for the digital core, the dynamic bypass capacitance equals a second bypass capacitance that is greater than the first bypass capacitance.

Abstract: Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.

Abstract: Disclosed is an apparatus and method for power efficient processor scheduling of features. In one embodiment, features may be scheduled for sequential computing, and each scheduled feature may receive a sensor data sample as input. In one embodiment, scheduling may be based at least in part on each respective feature's estimated power usage. In one embodiment, a first feature in the sequential schedule of features may be computed and before computing a second feature in the sequential schedule of features, a termination condition may be evaluated.