Patents by Inventor Rashmi Nagabhushana

Rashmi Nagabhushana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROCESSING UNIT, SOFTWARE MODULE, METHODS AND PROGRAM CODES
    Publication number: 20250190223
    Abstract: A device is provided. The device includes one or more interfaces configured to communicate with a plurality of random-access memories (RAM) and processing circuitry configured to control the one or more interfaces and to transmit a load message to each RAM of the plurality of RAM and determine a status of each RAM of the plurality of RAM.
    Type: Application
    Filed: April 12, 2022
    Publication date: June 12, 2025
    Inventors: Shihui LI, Ching Sia LIM, Rashmi NAGABHUSHANA, Krishna PAUL, Usharani AYYALASOMAYAJULA, Thomas TLUSTY
  • Methods and systems for streaming data packets on peripheral component interconnect (PCI) and on-chip bus interconnects
    Patent number: 11126572
    Abstract: A method and architecture to write data between a source and destination by memory mapped writes or streaming packets between any of a host, a peripheral or a sub-peripheral device. A stream address is used to write the data to a memory of the destination without the source being aware of physical addresses of destination memory, i.e., memory descriptors or pointers are not used, allowing the destination to manage its own memory. The stream address may enable streaming data packets over interconnects that may not allow packet streaming by dividing a data packet into data chunks and including a stream address for each chunk. The stream address for a given packet includes a repeated first portion indicating the destination and a varied second portion indicating variable information for each data chunk such as start of packet (SoP) and end of packet (EoP) identifiers.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 21, 2021
    Assignee: INTEL Corporation
    Inventors: Rashmi Nagabhushana, Raj Kumar Jain, Naveed Alam
  • METHODS AND SYSTEMS FOR STREAMING DATA PACKETS ON PERIPHERAL COMPONENT INTERCONNECT (PCI) AND ON-CHIP BUS INTERCONNECTS
    Publication number: 20190042489
    Abstract: A method and architecture to write data between a source and destination by memory mapped writes or streaming packets between any of a host, a peripheral or a sub-peripheral device. A stream address is used to write the data to a memory of the destination without the source being aware of physical addresses of destination memory, i.e., memory descriptors or pointers are not used, allowing the destination to manage its own memory. The stream address may enable streaming data packets over interconnects that may not allow packet streaming by dividing a data packet into data chunks and including a stream address for each chunk. The stream address for a given packet includes a repeated first portion indicating the destination and a varied second portion indicating variable information for each data chunk such as start of packet (SoP) and end of packet (EoP) identifiers.
    Type: Application
    Filed: February 13, 2018
    Publication date: February 7, 2019
    Inventors: Rashmi Nagabhushana, Raj Kumar Jain, Naveed Alam