Abstract: A computing system includes accelerator devices for hardware acceleration of operations of a fully homomorphic encryption (FHE) application, including a hybrid bootstrapping operation that may be parallelized for increased performance. Hybrid bootstrapping includes a first extraction on a first ciphertext (e.g., Ring Learning with Errors or RLWE) to form a plurality of second ciphertexts (e.g., LWE) corresponding to respective elements of the encrypted data, and a plurality of blind-rotate operations performed independently on the respective second ciphertexts to collectively produce a plurality of third ciphertexts (e.g., RLWE). A second extraction of respective elements of the third ciphertexts forms a plurality of fourth ciphertexts (e.g., LWE), and a repacking of respective elements of the fourth ciphertexts recreates the first-ciphertext representation of the encrypted data with restored modulus and reduced noise.

Abstract: An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.

Abstract: An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.

Abstract: An FPGA-based accelerator for bootstrappable fully homomorphic encryption (FHE) employs (1) acceleration of scalar arithmetic operations using a multi-word approach for efficient utilization of standard-width components (multipliers/adders) on custom-width operands; (2) a performant, shift-based modular reduction technique that avoids the need for expensive multipliers; (3) an improved datapath for an expensive Key Switch operation; and (4) an efficient organization of on-chip memory for storing custom-width operands and supplying them at high bandwidth to computation units.