Abstract: Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a method can comprise forming on a substrate a biasing loop and a flux controlled qubit device of a superconducting flux bias circuit. The method can further comprise forming a heating device on the substrate to couple the heating device to the biasing loop.

Abstract: Aspects of the invention include setting a fill mode for a border region of a layer of a macro of an integrated circuit. The border region has a depth defined by a multiple of the size of a tile used to select an area of the integrated circuit for implementation of a design rule check, and the fill mode indicates a fill percentage value or level of fill to be implemented in the border region of the layer of the macro. A fill of the border region of the layer of the macro is performed based on the fill mode. The integrated circuit is finalized and fabricated based on the performing of the fill and passing the design rule check.

Abstract: Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.

Abstract: Systems, computer-implemented methods, and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a first antenna can be positioned above a superconducting qubit chip having a first Josephson junction and a second Josephson junction. The first antenna can direct a first electromagnetic wave toward the first Josephson junction. A first length of a first defined vertical gap, between the first antenna and the superconducting qubit chip, can be sized to cause the first electromagnetic wave to circumscribe a first set of one or more capacitor pads of the first Josephson junction, thereby annealing the first Josephson junction, without annealing the second Josephson junction. In another example, the first length of the first defined vertical gap can be a function of a model of the first electromagnetic wave as a cone, wherein the cone originates from the first antenna and extends toward the superconducting qubit chip.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate quantum circuit topology selection based on frequency collisions between qubits, are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a simulation component that simulates operation of qubits in a subgraph topology of a graph representing a topology of a quantum circuit to determine a quantity of frequency collisions between the qubits. The computer executable components can further comprise a selection component that selects a quantum circuit topology based on the quantity of frequency collisions between the qubits.

Abstract: A method, computer system, and a computer program product for order compliance is provided. The present invention may include determining a shipping destination for an order request received from a user, wherein the order request includes one or more items. The present invention may include generating a digital twin for each of the one or more items in the order request. The present invention may include determining a compliance of the order request with a plurality of importation requirements of the shipping destination based on an analysis of the digital twin for each of the one or more items. The present invention may include generating a compliance report for the order request, wherein the compliance report includes at least a compliance status of each item included in the order request.

Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Abstract: Aspects of the invention include setting a fill mode for a border region of a layer of a macro of an integrated circuit. The border region has a depth defined by a multiple of the size of a tile used to select an area of the integrated circuit for implementation of a design rule check, and the fill mode indicates a fill percentage value or level of fill to be implemented in the border region of the layer of the macro. A fill of the border region of the layer of the macro is performed based on the fill mode. The integrated circuit is finalized and fabricated based on the performing of the fill and passing the design rule check.

Abstract: An apparatus for a fastening verification structure includes a fastener disposed in a cavity, where a leading end of the fastener is configured to press a non-insulated contact pad. The first end of a first lead electrically coupled to the fastener and a second end of the first lead electrically coupled to a power source. The first end of a second lead electrically coupled to the non-insulated contact pad and a second end of the second lead electrically coupled to a visual indicator. The first end of a third lead electrically coupled to the visual indicator and a second end of the third lead electrically coupled to the power source.

Abstract: Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: A method may include obtaining first ambient condition data corresponding to a first building in a first location. The method may further include obtaining a set of ice dam models. The method may further include predicting, based at least in part on the set of ice dam models, an ice dam formation on the first building. The method may further include obtaining a heating profile. The heating profile may be based at least in part on the first ambient condition data. The method may further include adjusting, based on the heating profile, a heating device of the first building.

Abstract: Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a method can comprise forming on a substrate a biasing loop and a flux controlled qubit device of a superconducting flux bias circuit. The method can further comprise forming a heating device on the substrate to couple the heating device to the biasing loop.

Abstract: Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a device can comprise a substrate having a superconducting flux bias circuit comprising a biasing loop coupled to a flux controlled qubit device. The device can further comprise a heating device coupled to the biasing loop.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.

Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.