Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a logical design for the semiconductor device and comparing an element in the logical design to a library of element patterns. The library of element patterns is derived by identifying layout patterns having electrical properties that deviate from modeled properties; the library also includes a quantitative measure of deviation from the modeled properties. In response to the comparing and with consideration of the quantitative measure, a determination is made as to whether the element is acceptable in the logical design. A mask set is generated that implements the logical design using either the element or a modified element if the element is not acceptable, and the mask set is employed to implement the logical design in and on a semiconductor substrate.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a logical design for the semiconductor device and comparing an element in the logical design to a library of element patterns. The library of element patterns is derived by identifying layout patterns having electrical properties that deviate from modeled properties; the library also includes a quantitative measure of deviation from the modeled properties. In response to the comparing and with consideration of the quantitative measure, a determination is made as to whether the element is acceptable in the logical design. A mask set is generated that implements the logical design using either the element or a modified element if the element is not acceptable, and the mask set is employed to implement the logical design in and on a semiconductor substrate.

Abstract: Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.

Abstract: Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.