Abstract: A storage system includes a plurality of storage servers that store a plurality of files, a monitor module, and a redirector module. The monitor module monitors usage information associated with the plurality of storage servers. The redirector module determines, based on the monitored usage information, a storage server in the plurality of storage servers to service a session from a client. The redirector module then instructs the client to establish the session with the determined storage server.

Abstract: File system independent techniques and mechanisms for replicating files on multiple devices are provided, migrating files from one device to another (for purposes of reliability, increased bandwidth, load balancing, capacity expansion, or reduced cost), and propagating updates from a master copy to remote replicas. The mechanisms involve work queues and asynchronous file migration daemons that operate independently from and in parallel with the primary client-server and network protocol to on-disk storage data paths.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: A control memory is provided for storing the control and state information of a number of virtual direct memory access (DMA) channels. A control memory arbiter and a control memory data bus are also provided to arbitrate accesses to the control memory to facilitate asynchronous transmit and receive. Separate areas in the control memory are provided for storing the control and state information of the transmit DMAs, and the receive DMAs. Additionally, descriptive information about the transmit/receive data ring and its descriptor, the data packet being transferred and its cells are also stored for the transmit and receive DMAs. The control memory is also used to stored a programmable bandwidth group (BWG) table comprising a plurality of BWG index entries for bandwidth selection.

Abstract: A method and apparatus for interfacing between a Segmentation and Reassembly (SAR) circuit and an ATM Cell Interface is disclosed. The interface circuit comprises a transmit FIFO and a receive FIFO. The transmit FIFO transfers data from the System and ATM Layer Core in the SAR circuit to a Cell Interface block, which in turn dispatches the data to the ATM Cell Interface. The receive FIFO transfers data received from the ATM Cell Interface via the Cell Interface block, to the Core. Various interface signals provided between the Core and the transmit FIFO, the transmit FIFO and the Cell Interface block, the Core and the receive FIFO, and the receive FIFO and the Cell Interface block, are used to coordinate data transfer. The interface circuit insulates the Core from the ATM Cell Interface, allowing the Core to operate independently from ATM Cell Interface specifics.

Abstract: An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache.

Abstract: A number of storage units and a number of state machines are provided to reorder interleaved ATM data cells for a number of channels incoming to a networked host computer. The storage units store the incoming ATM data cells, a number of data structures tracking the stored ATM data cells for the channels and the free resources, and an unload schedule queue. The state machines load and unload the incoming ATM data cells, and update the tracking data structures and schedule queue accordingly.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: A method and an apparatus for reducing data copying overhead associated with protected memory operating systems. In an ATM (Asynchronous Transfer Method) network, the present invention's NIC (network interface circuit) demultiplexes the information in the header of the incoming packet and routes the packet directly to its final destination using the present invention's concept of targeted buffer rings. Thus, instead of having the packet be DMA'd to a buffer in a descriptor ring in the kernel, it may be routed directly to the buffer ring of the destination process.

Abstract: A network interface circuit (NIC) is provided with logic for maintaining various control pointers and at least one control counter for controlling burst transferring of buffered ATM cells to its host computer system in a non-cellboundary-aligned block manner, distinguishing the ATM packet header from the ATM data most of the time, except for a number of predetermined exceptions. More specifically, ATM packet headers and ATM data are to be burst transferred to separate header and data buffers on the host computer system, except for short and atypical packets, in fixed size blocks, where the block size is complementary to the interface bus, but not necessarily aligned with the ATM cell boundaries. For the short and atypical packets, both the header and data are to be burst transferred into the header buffer instead.

Abstract: A method and apparatus of reporting the status of data transfer between software and hardware in a computer system is disclosed. Software provides empty descriptors to the hardware for posting completion updates of transfers. More particularly, the software provides the number of the last available descriptor to a first storage field in a storage location which is accessible to the hardware. The hardware accounts for the number of the descriptors it has used for reporting completion updates by posting the number of used descriptors to a second storage field in the storage location. To determine if more descriptors are available, the hardware compares the contents of the first storage field to that of the second storage field. If the contents of the first and second storage fields are equal, the hardware has reached the last descriptor in the completion ring. If the fields are not equal, one or more descriptors are available for the hardware to use.

Abstract: A generic Input/Output interface between an IO block and a System and ATM Layer Core on a network interface circuit is provided. The GIO interface includes parallel DMA read and write control handshake signal lines; parallel DMA read and write data handshake signal lines which operate independently from the read and write control handshake signal lines; parallel DMA read and write data signal lines; and a single clock signal line. GIO interface facilitates maximum utilization of the IO bandwidth, and allows several requests to be queued across the GIO interface at the same time, in each read and write direction. In addition, the GIO interface utilizes a fixed clock for driving the transmit and receive data path. By thus referencing all transactions to a clock driving the Core, the Core remains unchanged for different embodiments of the network interface circuit which interface to different host computer systems and busses.

Abstract: A network interface card (NIC) is provided with a transmit unload block for asynchronously segmenting packet data into ATM cells for packets of multiple channels. The transmit unload block comprises a cellification block and a cellification and DMA scheduler. The cellification block is used to perform the actual cellification of the packet data into ATM cells, one ATM cell at a time, and management of the packet control data associated with the ATM cell's packet as well as management of the buffer control data associated with the ATM cell's channel. The construction of the current ATM cell is overlapped with the management of the packet and buffer control data associated with the immediately preceding ATM cell. The cellification and DMA scheduler is used to control the operation of the cellification block. The cellification and DMA scheduler is also used to schedule DMAs to obtain additional packet data for the channels.

Abstract: A method and apparatus of coordinating data transfer between hardware and software in a computer system through the use of a semaphore mechanism is disclosed. When a data packet is queued by preparing an entry in a data descriptor ring, software provides the descriptor entry number to a first storage field in a predetermined storage location which is accessible by hardware. Hardware accounts for the transactions it has completed by writing the descriptor entry number to a second storage field in the storage location. To determine if there is additional data to process, hardware compares the contents of the first storage field and the contents of the second storage field. If the contents of both storage fields are equal, the corresponding ring or channel has run out of data and no additional data is to be processed.

Abstract: A method and an apparatus for verifying a network transporter under test which is able to perform the test and produce test results by posting test packets through network transporter without requiring large amounts of memory and producing results in a short period of time. The present invention utilizes one or more FIFO (First In First Out) buffers in which plurality of components of each packet is stored just as each packet is posted to the network transporter under test. As soon as the corresponding packet is received on the other side of the network transporter, plurality of components and the receive packet are compared and a test result is produced. As soon as such comparison is performed and completed and the test results are produced, the corresponding plurality of components stored in the FIFO is discarded and the corresponding memory space used is freed up for the next packet's test information.

Abstract: A transmission data buffer and method for buffering data to be transmitted from a host computer to an asynchronous transfer mode (ATM) telecommunications network. The transmission data buffer comprises a plurality if FIFO memories, one for each channel which is established on the connection to the ATM network. A load engine loads packets of data (e.g. AAL5, AAL5-MPEG, TCP packets) into particular FIFO memories in the transmission buffer according to a load schedule queue. The data is removed from the FIFO memories by an unload engine according to entries in a bandwidth group table. The unload engine segments the data as it is removed from the FIFOs, by removing one ATM cell payload (48-bytes) at a time, and adds the ATM cell header data. The unload engine can also generate AAL5 packet CRC fields and add a control and length field to the cell data segmented from an AAL5 packet.

Abstract: Interrupts are presented to a processor to indicate the arrival of data packets from a high speed network. The rate of packet arrival interrupts is modulated to prevent burdening the processor unnecessarily with repeated interrupts while receiving a burst of data. The interrupt modulator of the present invention ensures that the first packet of a new data burst, or the first packet of a short message, generate an immediate interrupt to the processor, thus avoiding any unnecessary latency in the processor's response. This is done by enabling a packet arrival to generate an interrupt if a specified period of time has elapsed since the previous interrupt. Further, the interrupt modulator ensures that every N'th packet that arrives generates an interrupt--for example, to ensure that the processor performs any memory management functions that may be required. A packet does not generate an interrupt if it arrives soon enough after the previous interrupt and it is not the N'th packet since the pervious interrupt.

Abstract: A method and network interface for controlling the flow of data between a and an ATM network is provided. The network interface resides on an ATM interface and includes a state machine for each channel supported by the ATM interface. The state machine moves from state to state based on the contents of a local buffer, indications that data for the channel is ready to be transferred from the host computer to the local buffer, and the status of operations that transfer data for the channel from the host computer to the local buffer. The ATM interface includes a DMA unit and a segmentation unit that operate responsive to the states of the various state machines to avoid inefficient transfer operations.

Abstract: The asynchronous transfer mode (ATM) interface, which may be a segmentation and reassembly unit, controls segmentation of packets into cells and reassembly of cells into packets for interconnecting a computer system to an ATM system. An architecture is disclosed which partitions load and unload functions within the ATM interface. The load and unload functions are separately partitioned for segmentation and for reassembly. For segmentation, a transmit load engine controls storage of data from packets into an external buffer memory; whereas transmit unload engine handles extracting data from the memory, segmenting the data into cells, and transmitting the cells to the ATM system. For reassembly, a receive load engine handles receiving and storing the cells corresponding to the packets into a memory; whereas a receive unload engine controls extraction of the data from the memory and transmission of the packets to the computer system.