Patents by Inventor Ratan Deep H. Singh

Ratan Deep H. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8190953
    Abstract: A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of failed test vectors.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: May 29, 2012
    Inventors: Sameer H. Chakravarthy, Ratan Deep H. Singh, Thomas Webster Bartenstein, Joseph Michael Swenton, Shaleen Bhabu
  • Publication number: 20100088560
    Abstract: A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of tailed test vectors.
    Type: Application
    Filed: October 3, 2008
    Publication date: April 8, 2010
    Inventors: Sameer H. Chakravarthy, Ratan Deep H. Singh, Thomas Webster Bartenstein, Joseph Michael Swenton, Shaleen Bhabu