Patents by Inventor Ratheesh R. Thankalekshmi

Ratheesh R. Thankalekshmi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails
    Patent number: 10332897
    Abstract: Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaoqiang Zhang, Hui Zang, Ratheesh R. Thankalekshmi, Randy W. Mann
  • METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS
    Publication number: 20190019798
    Abstract: Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.
    Type: Application
    Filed: September 17, 2018
    Publication date: January 17, 2019
    Inventors: Xiaoqiang Zhang, Hui Zang, Ratheesh R. Thankalekshmi, Randy W. Mann
  • Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
    Patent number: 10163914
    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaoqiang Zhang, Hui Zang, Ratheesh R. Thankalekshmi, Randy W. Mann
  • METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS
    Publication number: 20180261605
    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.
    Type: Application
    Filed: May 24, 2017
    Publication date: September 13, 2018
    Inventors: Xiaoqiang Zhang, Hui Zang, Ratheesh R. Thankalekshmi, Randy W. Mann