Abstract: A process for forming an insulating layer of silicon dioxide in a silicon substrate that surrounds and electrically insulates a semiconductor device is disclosed herein. The process comprises the steps of forming a recess on the outer surface of the silicon substrate that encompasses the site of the semiconductor device by photo-resist patterned reactive ion etching, and then removing silicon on the surface of the resulting recess whose crystal structure has been damaged by the reactive ion etching. Next, dopant atoms are selectively deposited on the surface of the recess so that the surface of the recess might be rendered into a porous layer of silicon when immersed in hydrogen fluoride and subjected to an electrical current. Prior to the porousification step, silicon is epitaxially grown within the walls of the recess to form the site for a semiconductor device.

Abstract: A method of fabrication of an electrical connection between two vertically spaced conducting layers in an integrated circuit structure. The first conducting layer is a selected area of the semiconductive substrate which is otherwise covered with a dielectric layer. The exposed selected area of the semiconductive substrate is treated with an activation agent and a selected conductor is chemically vapor deposited upon the activated selected area of the semiconductive substrate. The selected conductor interconnect is built up in successive chemical vapor deposition steps preceded by activation treatment of the exposed top surface until the conductor interconnect is approximately equal to the thickness of the dielectric layer and has a highly planar surface upon which can be readily deposited the second conductive layer which is thus interconnected to the semiconductor substrate.