Abstract: A chip layout system lays out chips including adjustable-shaped domains of standard cells and fixed-size macrocells. The system orders those standard cells which have interconnections into binary pairs or groupings of two. The binary pairs are grouped in higher and higher order groupings based upon evaluations of the area of the grouping and the sum of the lengths of the interconnections. All possible permutations of placement configuration including some rotations of various elements are further evaluated and the final placement is established on the basis of a minimum area, minimum interconnect length criterion. During the processing, the aspect ratios of the various domains and grouping of domains are adjusted to optimize their placement on the chip surface.

Abstract: An automated LSI chip layout arrangement includes automated layout of the power bus distribution network. A complete interlocking mesh of buses is run in routing channels lying between groups of circuits to be powered. Each segment of the mesh powering net which affects the chip size is tested to see if it can be removed without adversely affecting the power distribution. If it can be removed, the segment is deleted. The next segment which is critical to the size of the chip is then tested, and the process is continued. Those segments of the power bus distribution network which do not affect the size of the chip are not eliminated. Thus, a low-resistance power distribution bus network is guaranteed, and chip size is minimized.