Patents by Inventor Ratibor Radojcic

Ratibor Radojcic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971476
    Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim
  • Patent number: 9881859
    Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Jae Sik Lee, Shiqun Gu, Ratibor Radojcic
  • Patent number: 9869713
    Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: January 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sung Kyu Lim, Ratibor Radojcic, Yang Du
  • Patent number: 9853446
    Abstract: An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: December 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Eugene Robert Worley, Ratibor Radojcic, Urmi Ray
  • Patent number: 9704796
    Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Shree Krishna Pandey, Ratibor Radojcic
  • Patent number: 9633977
    Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Shiqun Gu, Urmi Ray, Ratibor Radojcic
  • Publication number: 20170063079
    Abstract: An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 2, 2017
    Inventors: Shiqun Gu, Eugene Robert Worley, Ratibor Radojcic, Urmi Ray
  • Publication number: 20170005160
    Abstract: Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.
    Type: Application
    Filed: December 17, 2015
    Publication date: January 5, 2017
    Inventors: Shiqun GU, Yue LI, Ratibor RADOJCIC
  • Publication number: 20160258996
    Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 8, 2016
    Inventors: Sung Kyu Lim, Ratibor Radojcic, Yang Du
  • Patent number: 9418877
    Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: August 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim, Jae Sik Lee
  • Publication number: 20160133614
    Abstract: The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Shiqun GU, Ratibor RADOJCIC, Mustafa BADAROGLU, Chunlei SHI, Yuancheng Christopher PAN
  • Patent number: 9285418
    Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Tapan J Chakraborty, Rajamani Sethuram, Ratibor Radojcic
  • Publication number: 20150325509
    Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Jae Sik Lee, Shiqun Gu, Ratibor Radojcic
  • Publication number: 20150318262
    Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.
    Type: Application
    Filed: July 4, 2014
    Publication date: November 5, 2015
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim, Jae Sik Lee
  • Patent number: 9136202
    Abstract: An apparatus has external and/or internal capacitive thermal material for enhanced thermal package management. The apparatus includes an integrated circuit (IC) package having a heat generating device. The apparatus also includes a heat spreader having a first side that is attached to the IC package. The apparatus also includes capacitive thermal material reservoirs contacting the first side of the heat spreader. The capacitive thermal material reservoirs may be disposed laterally relative to the heat generating device.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: September 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Victor A. Chiriac, Durodami J. Lisk, Ratibor Radojcic
  • Publication number: 20150235991
    Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 20, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim
  • Publication number: 20150214127
    Abstract: Some features pertain to an integrated device that includes a substrate. The substrate includes a first cavity (e.g., trench). The first cavity includes a first edge that is non-vertical. The first cavity is configured to align a die towards a center of the first cavity when the die is placed off-center of the first cavity. The integrated device also includes a first die positioned in the first cavity. The integrated device further includes a redistribution portion coupled to the first die. In some implementations, the first edge is a first wall of the first cavity. In some implementations, the first cavity includes a first opening and a first base portion. The first opening of the first cavity is greater than the first base portion of the first cavity.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim
  • Publication number: 20140306349
    Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 16, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Urmi Ray, Roawen Chen, Brian Matthew Henderson, Ratibor Radojcic, Matthew Nowak, Nicholas Yu
  • Publication number: 20140225246
    Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 14, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Brian Matthew Henderson, Durodami Joscelyn Lisk, Shiqun Gu, Ratibor Radojcic, Matthew Michael Nowak
  • Patent number: 8803305
    Abstract: A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: August 12, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ratibor Radojcic, Arvind Chandrasekaran, Ryan Lane