Patents by Inventor Ratmir Gelagaev

Ratmir Gelagaev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voltage clamping circuit and use thereof
    Patent number: 9000791
    Abstract: A voltage clamp circuit for reflecting a voltage at an input node includes a circuit for providing at least two currents at its output terminal, and at least two diodes each being connected to an output terminal of the circuit for providing at least two currents. The diodes also are connected to a line of a ground voltage and to the input node respectively. The circuit includes an alternative current path connected to an output terminal of the circuit for providing at least two currents and to a current sinking node. The voltage at the input node thus is reflected as the voltage between two output nodes when the voltage at the input node is lower than a clamping voltage and so that the voltage is fixed between the two output nodes to the clamping voltage when the voltage at the input node is higher than the clamping voltage.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 7, 2015
    Assignees: Katholieke Universiteit Leuven, Triphase
    Inventors: Johan Driesen, Jordi Everts, Ratmir Gelagaev, Pieter Jacqmaer, Jeroen Van den Keybus
  • VOLTAGE CLAMPING CIRCUIT AND USE THEREOF
    Publication number: 20130049783
    Abstract: A voltage clamp circuit for reflecting a voltage at an input node includes a circuit for providing at least two currents at its output terminal, and at least two diodes each being connected to an output terminal of the circuit for providing at least two currents. The diodes also are connected to a line of a ground voltage and to the input node respectively. The circuit includes an alternative current path connected to an output terminal of the circuit for providing at least two currents and to a current sinking node. The voltage at the input node thus is reflected as the voltage between two output nodes when the voltage at the input node is lower than a clamping voltage and so that the voltage is fixed between the two output nodes to the clamping voltage when the voltage at the input node is higher than the clamping voltage.
    Type: Application
    Filed: April 29, 2011
    Publication date: February 28, 2013
    Inventors: Johan Driesen, Jordi Everts, Ratmir Gelagaev, Pieter Jacqmaer, Jeroen Van den Keybus