Patents by Inventor Ratson Morad

Ratson Morad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070215197
    Abstract: A solar cell unit having a solar cell and a transparent casing circumferentially disposed onto the solar cell is provided. The solar cell has a substrate, where at least a portion of the substrate is rigid and nonplanar. A back-electrode is circumferentially disposed on the substrate. A semiconductor junction layer is circumferentially disposed on the back-electrode. A transparent conductive layer is circumferentially disposed on the semiconductor junction.
    Type: Application
    Filed: May 3, 2007
    Publication date: September 20, 2007
    Inventors: Benyamin Buller, Christian Gronet, Ratson Morad, Markus Beck
  • Publication number: 20070215195
    Abstract: A solar cell unit comprising a cylindrical shaped solar cell and a transparent tubular casing is provided. The tubular shaped solar cell comprises a back-electrode, a semiconductor junction circumferentially disposed on the back-electrode and a transparent conductive layer disposed on the semiconductor junction. The transparent tubular casing is circumferentially sealed onto the transparent conductive layer of the cylindrical shaped solar cell. A solar cell unit comprising a cylindrical shaped solar cell, a filler layer, and a transparent tubular casing is provided. The cylindrical shaped solar cell comprises a cylindrical substrate, a back-electrode circumferentially disposed on the cylindrical substrate, a semiconductor junction circumferentially disposed on the back-electrode, and a transparent conductive layer disposed on the semiconductor junction.
    Type: Application
    Filed: March 18, 2006
    Publication date: September 20, 2007
    Inventors: Benyamin Buller, Chris Gronet, Ratson Morad, Markus Beck
  • Publication number: 20070128869
    Abstract: A method and apparatus for annealing copper. The method comprises forming a copper layer by electroplating on a substrate in an integrated processing system and annealing the copper layer in a chamber inside the integrated processing system.
    Type: Application
    Filed: February 2, 2007
    Publication date: June 7, 2007
    Inventors: B. Chen, Ho Shin, Yezdi Dordi, Ratson Morad, Robin Cheung
  • Patent number: 7192494
    Abstract: A method and apparatus for annealing copper. The method comprises forming a copper layer by electroplating on a substrate in an integrated processing system and annealing the copper layer in a chamber inside the integrated processing system.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 20, 2007
    Assignee: Applied Materials, Inc.
    Inventors: B. Michelle Chen, Ho Seon Shin, Yezdi Dordi, Ratson Morad, Robin Cheung
  • Publication number: 20060246690
    Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.
    Type: Application
    Filed: June 27, 2006
    Publication date: November 2, 2006
    Inventors: Yezdi Dordi, Donald Olgado, Ratson Morad, Peter Hey, Mark Denome, Michael Sugarman, Mark Lloyd, Anna Lloyd, Joseph Stevens, Dan Marohl, Ho Shin, Eugene Ravinovich, Robin Cheung, Ashok Sinha, Avi Tepman, Dan Carl, George Birkmaier
  • Patent number: 7104869
    Abstract: The invention generally provides methods and compositions for planarizing a substrate surface having underlying dielectric materials. Aspects of the invention provide compositions and methods using a combination of low polishing pressures, polishing compositions, various polishing speeds, selective polishing pads, and selective polishing temperatures, for removing barrier materials by a chemical mechanical polishing technique with minimal residues and minimal seam damage. Aspects of the invention are achieved by employing a strategic multi-step process including sequential CMP at low polishing pressure to remove the deposited barrier materials.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 12, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Stan Tsai, Rashid Mavliev, Lizhong Sun, Feng Q. Liu, Liang-Yuh Chen, Ratson Morad
  • Publication number: 20060166487
    Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.
    Type: Application
    Filed: March 30, 2006
    Publication date: July 27, 2006
    Inventors: Stan Tsai, Liang-Yuh Chen, Lizhong Sun, Shijian Li, Feng Liu, Rashid Mavliev, Ratson Morad, Daniel Carl
  • Patent number: 7060606
    Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: June 13, 2006
    Assignee: Applied Materials Inc.
    Inventors: Stan D. Tsai, Liang-Yuh Chen, Lizhong Sun, Shijian Li, Feng Q. Liu, Rashid Mavliev, Ratson Morad, Daniel A. Carl
  • Patent number: 6979248
    Abstract: An article of manufacture, method, and apparatus are provided for planarizing a substrate surface. In one aspect, an article of manufacture is provided for polishing a substrate including a polishing article having a body comprising at least a portion of fibers coated with a conductive material, conductive fillers, or combinations thereof, and adapted to polish the substrate. In another aspect, a polishing article includes a body having a surface adapted to polish the substrate and at least one conductive element embedded in the polishing surface, the conductive element comprising dielectric or conductive fibers coated with a conductive material, conductive fillers, or combinations thereof. The conductive element may have a contact surface that extends beyond a plane defined by the polishing surface. A plurality of perforations and a plurality of grooves may be formed in the articles to facilitate flow of material through and around the polishing article.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: December 27, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Yongqi Hu, Yan Wang, Alain Duboust, Feng Q. Liu, Rashid Mavliev, Liang-Yuh Chen, Ratson Morad, Sasson Somekh
  • Publication number: 20050282380
    Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.
    Type: Application
    Filed: October 22, 2004
    Publication date: December 22, 2005
    Inventors: Stan Tsai, Liang-Yuh Chen, Lizhong Sun, Shijian Li, Feng Liu, Rashid Mavliev, Ratson Morad, Daniel Carl
  • Patent number: 6977036
    Abstract: A method and apparatus are provided for polishing a substrate surface. In one aspect, an apparatus for polishing a substrate includes a conductive polishing pad and an electrode having a membrane disposed therebetween. The membrane is orientated relative the conductive pad in a manner that facilitates removal of entrained gas from electrolyte flowing towards the conductive pad. The apparatus may be part of an electro-chemical polishing station that may optionally be part of a system that includes chemical mechanical polishing stations.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: December 20, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Ralph Wadensweiler, Alain Duboust, Liang-Yuh Chen, Manoocher Birang, Ratson Morad, Paul D. Butterfield
  • Publication number: 20050221603
    Abstract: Provided herein is a system architecture of semiconductor manufacturing equipment, wherein degas chamber(s) are integrated to the conventional pass-through chamber location. Also provided herein is a system/method for depositing Cu barrier and seed layers on a semiconductor wafer. This system comprises a front opening unified pod(s), a single wafer loadlock chamber(s), a degas chamber(s), a preclean chamber(s), a Ta or TaN process chamber(s), and a Cu process chamber(s). The degas chamber is integrated to a pass-through chamber. Such system may achieve system throughput higher than 100 wafers per hour.
    Type: Application
    Filed: May 24, 2005
    Publication date: October 6, 2005
    Inventors: Ratson Morad, Ho Seon Shin
  • Publication number: 20050202677
    Abstract: Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.
    Type: Application
    Filed: April 25, 2005
    Publication date: September 15, 2005
    Inventors: Wei-Yung Hsu, Liang-Yuh Chen, Ratson Morad, Daniel Carl
  • Patent number: 6929774
    Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: August 16, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Ratson Morad, Ho Seon Shin, Robin Cheung, Igor Kogan
  • Patent number: 6896776
    Abstract: A method and apparatus is provided for depositing and planarizing a material layer on a substrate. In one embodiment, an apparatus is provided which includes a partial enclosure, a permeable disc, a diffuser plate and optionally an anode. A substrate carrier is positionable above the partial enclosure and is adapted to move a substrate into and out of contact or close proximity with the permeable disc. The partial enclosure and the substrate carrier are rotatable to provide relative motion between a substrate and the permeable disc. In another aspect, a method is provided in which a substrate is positioned in a partial enclosure having an electrolyte therein at a fist distance from a permeable disc. A current is optionally applied to the surface of the substrate and a first thickness is deposited on the substrate. Next, the substrate is positioned closer to the permeable disc and a second thickness is deposited on the substrate.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: May 24, 2005
    Assignee: Applied Materials Inc.
    Inventors: Wei-Yung Hsu, Liang-Yuh Chen, Ratson Morad, Daniel A. Carl, Sasson Somekh
  • Patent number: 6897146
    Abstract: A semiconductor manufacturing equipment wherein degas chamber(s) are integrated to the conventional pass-through chamber location. A preferred embodiment for depositing Cu barrier and seed layers on a semiconductor wafer comprises a front opening unified pod(s), a single wafer loadlock chamber(s), a degas chamber(s), a preclean chamber(s), a Ta or TaN process chamber(s), and a Cu process chamber(s). The degas chamber is integrated to a pass-through chamber. Such system may achieve system throughput higher than 100 wafers per hour.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: May 24, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Ratson Morad, Ho Seon Shin
  • Patent number: 6893548
    Abstract: An apparatus and method is provided for analyzing or conditioning an electrochemical bath. One aspect of the invention provides a method for analyzing an electrochemical bath in an electrochemical deposition process including providing a first electrochemical bath having a first bath composition, utilizing the first electrochemical bath in an electrochemical deposition process to form a second electrochemical bath having a second bath composition and analyzing the first and second compositions to identify one or more constituents generated in the electrochemical deposition process. Additive material having a composition that is substantially the same as all or at least some of the one or more constituents generated in the electrochemical deposition process may be added to another electrochemical bath to produce a desired chemical composition.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: May 17, 2005
    Assignee: Applied Materials Inc.
    Inventors: Robin Cheung, Daniel A. Carl, Liang-Yuh Chen, Yezdi Dordi, Paul F. Smith, Ratson Morad, Peter Hey, Ashok Sinha
  • Patent number: 6884724
    Abstract: Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: April 26, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Yung Hsu, Liang-Yuh Chen, Ratson Morad, Daniel A. Carl
  • Publication number: 20050056537
    Abstract: A method and apparatus are provided for planarizing a material layer on a substrate. In one aspect, a method is provided for processing a substrate including forming a passivation layer on a substrate surface, polishing the substrate in an electrolyte solution, applying an anodic bias to the substrate surface, and removing material from at least a portion of the substrate surface. In another aspect, an apparatus is provided which includes a partial enclosure, polishing article, a cathode, a power source, a substrate carrier movably disposed above the polishing article, and a computer based controller to position a substrate in an electrolyte solution to form a passivation layer on a substrate surface, to polish the substrate in the electrolyte solution with the polishing article, and to apply an anodic bias to the substrate surface or polishing article to remove material from at least a portion of the substrate surface.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 17, 2005
    Inventors: Liang-Yuh Chen, Wei-Yung Hsu, Alain Duboust, Ratson Morad, Daniel Carl
  • Patent number: 6841057
    Abstract: A method and apparatus are provided for polishing a substrate surface. In one aspect, an apparatus for polishing a substrate includes a conductive polishing pad and an electrode having a membrane disposed therebetween. The membrane is orientated relative the conductive pad in a manner that facilitates removal of entrained gas from electrolyte flowing towards the conductive pad. The apparatus may be part of an electro-chemical polishing station that may optionally be part of a system that includes chemical mechanical polishing stations.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 11, 2005
    Assignee: Applied Materials Inc.
    Inventors: Ralph Wadensweiler, Alain Duboust, Liang-Yuh Chen, Manoocher Birang, Ratson Morad, Paul D. Butterfield