Patents by Inventor Raul Andres Bianchi

Raul Andres Bianchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12342641
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Grant
    Filed: June 14, 2024
    Date of Patent: June 24, 2025
    Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres Bianchi, Marios Barlas, Alexandre Lopez, Bastien Mamdy, Bruce Rae, Isobel Nicholson
  • Publication number: 20250022894
    Abstract: A pixel includes, on a first face, first trenches extending parallel to a first direction and regularly spaced in a second direction (orthogonal to the first direction) and second trenches extending parallel to the second direction and regularly spaced in the first direction. The first trenches include first notches, each first notch extending from a first trench and being aligned with a corresponding second trench. The second trenches include second notches, each second notch extending from a second trench and being aligned with a corresponding first trench.
    Type: Application
    Filed: July 1, 2024
    Publication date: January 16, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Giulio FORCOLIN, Raul Andres BIANCHI, Isobel NICHOLSON
  • Publication number: 20240405146
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
  • Publication number: 20240393439
    Abstract: The present disclosure relates to a process to control an optoelectronic device comprising a single-photon avalanche diode n a substrate, wherein the diode comprises a first region doped with a first type of conductivity level with a first face of the substrate and a second region doped with a second type of conductivity extending from the first face to a second face of the substrate opposed to the first face, wherein the device comprises a third conducting or semiconducting region at the second face, wherein the process comprises the application of a biasing voltage to the third region in order to generate an electric field that accelerates the charges generated in the diode.
    Type: Application
    Filed: May 22, 2024
    Publication date: November 28, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Raul Andres BIANCHI, Christel Marie-Noëlle BUJ
  • Publication number: 20240339464
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 10, 2024
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
  • Publication number: 20240334087
    Abstract: The present disclosure relates to an avalanche photodiode pixel including: a transistor adapted to be controlled by an enable signal having a first state for controlling the enabling of the pixel and a second state for controlling the disabling of the pixel, the transistor being configured to couple an avalanche photodiode of the pixel to a node of application of a substrate voltage when the enable signal is in the first state; and an output circuit adapted to be controlled by the enable signal and configured to provide a pixel output signal when the enable signal is in the first state and to block the pixel output signal when the enable signal is in the second state.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Raffaele BIANCHINI, Raul Andres BIANCHI, Mohammed AL-RAWHANI
  • Patent number: 12087873
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin Zimmer, Dominique Golanski, Raul Andres Bianchi
  • Patent number: 12087708
    Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
  • Patent number: 12051705
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 30, 2024
    Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres Bianchi, Marios Barlas, Alexandre Lopez, Bastien Mamdy, Bruce Rae, Isobel Nicholson
  • Patent number: 11495609
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 8, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Publication number: 20220310867
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 29, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
  • Patent number: 11336853
    Abstract: The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: May 17, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Raul Andres Bianchi, Matteo Maria Vignetti, Bruce Rae
  • Publication number: 20220085084
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 17, 2022
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
  • Publication number: 20220045020
    Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.
    Type: Application
    Filed: October 21, 2021
    Publication date: February 10, 2022
    Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
  • Patent number: 11183468
    Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 23, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
  • Publication number: 20210105427
    Abstract: The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 8, 2021
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Raul Andres BIANCHI, Matteo Maria VIGNETTI, Bruce RAE
  • Publication number: 20210057426
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
  • Patent number: 10833027
    Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 10, 2020
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
  • Patent number: 10833094
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Patent number: 10281512
    Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 7, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
    Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa