Patents by Inventor Raul Andres Bianchi
Raul Andres Bianchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495609Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: GrantFiled: November 9, 2020Date of Patent: November 8, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
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Publication number: 20220310867Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.Type: ApplicationFiled: March 23, 2022Publication date: September 29, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
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Patent number: 11336853Abstract: The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.Type: GrantFiled: October 5, 2020Date of Patent: May 17, 2022Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Raul Andres Bianchi, Matteo Maria Vignetti, Bruce Rae
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Publication number: 20220085084Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.Type: ApplicationFiled: September 9, 2021Publication date: March 17, 2022Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SASInventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
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Publication number: 20220045020Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
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Patent number: 11183468Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.Type: GrantFiled: June 30, 2017Date of Patent: November 23, 2021Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
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Publication number: 20210105427Abstract: The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.Type: ApplicationFiled: October 5, 2020Publication date: April 8, 2021Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Raul Andres BIANCHI, Matteo Maria VIGNETTI, Bruce RAE
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Publication number: 20210057426Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: ApplicationFiled: November 9, 2020Publication date: February 25, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
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Patent number: 10833027Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.Type: GrantFiled: October 16, 2017Date of Patent: November 10, 2020Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
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Patent number: 10833094Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: GrantFiled: April 17, 2018Date of Patent: November 10, 2020Assignee: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
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Patent number: 10281512Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.Type: GrantFiled: December 21, 2016Date of Patent: May 7, 2019Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
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Patent number: 10217503Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.Type: GrantFiled: October 4, 2018Date of Patent: February 26, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
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Publication number: 20190035450Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
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Patent number: 10127966Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.Type: GrantFiled: December 23, 2016Date of Patent: November 13, 2018Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
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Publication number: 20180277496Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.Type: ApplicationFiled: October 16, 2017Publication date: September 27, 2018Inventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
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Publication number: 20180233511Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: ApplicationFiled: April 17, 2018Publication date: August 16, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
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Patent number: 9978764Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: GrantFiled: April 20, 2016Date of Patent: May 22, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
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Publication number: 20180061781Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.Type: ApplicationFiled: June 30, 2017Publication date: March 1, 2018Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
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Publication number: 20180003761Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.Type: ApplicationFiled: December 21, 2016Publication date: January 4, 2018Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
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Publication number: 20180005684Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.Type: ApplicationFiled: December 23, 2016Publication date: January 4, 2018Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa