Abstract: A floating platform for high-power wind turbines, comprising a concrete substructure, said concrete substructure forming the base of the platform, which remains semi-submerged in the operating position, and consisting of a square lower slab on which a series of beams and five hollow reinforced concrete cylinders are constructed, distributed at the corners and the center of said lower slab; a metal superstructure supported on the concrete substructure and forming the base for connection with the wind turbine tower, said tower being coupled at the center thereof; and metal covers covering each of the cylinders, on which the metal superstructure is supported and to which vertical pillars are secured, linked together by beams, which join at the central pillar by an element whereon the base of the wind turbine tower is secured.

Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.