Abstract: An electronic device includes a multilevel lamination structure having a core layer, dielectric layers and conductive features formed in metal layers on or between respective ones or pairs of the dielectric layers. The core layer and the dielectric layers extend in respective planes of orthogonal first and second directions and are stacked along an orthogonal third direction. The conductive features include a first patterned conductive feature having multiple conductive turns in each of a first pair of the metal layers to form a first winding having a first turn and a final turn adjacent to one another in the same metal layer of the first pair, and a second patterned conductive feature having multiple conductive turns in a second pair of the metal layers to form a second winding having a first turn and a final turn.