Abstract: An array of memory cells of an integrated circuit are organized so metal bitlines are segmented. The memory cells may be nonvolatile memory cells such as floating gate, Flash, EEPROM, and EPROM cells. The bitlines for the memory cells are strapped to metal, and the metal bitline is segmented. The individual segments may be selectively connected to voltages as desired to allow configuring (e.g., programming) or reading of the memory cells. The programming voltage may be a high voltage, above the VCC of the integrated circuit. By dividing the metal bitlines into segments, this reduces noise between bitlines and improve the performance and reliability, and reduce power consumption because the parasitic capacitances are reduced compared to a long metal bitline (i.e., where all the segments are connected together and operated as one).

Abstract: A memory system (e.g., memory card) for reading and programming (writing) of dual cell memory elements is disclosed. According to one aspect of the invention, all bit lines for the memory system can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

Abstract: A memory system (e.g., memory card) for reading and programming (writing) of dual cell memory elements is disclosed. According to one aspect of the invention, all bit lines for the memory system can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

Abstract: An array of memory cells of an integrated circuit are organized so metal bitlines are segmented. The memory cells may be nonvolatile memory cells such as floating gate, Flash, EEPROM, and EPROM cells. The bitlines for the memory cells are strapped to metal, and the metal bitline is segmented. The individual segments may be selectively connected to voltages as desired to allow configuring (e.g., programming) or reading of the memory cells. The programming voltage may be a high voltage, above the VCC of the integrated circuit. By dividing the metal bitlines into segments, this reduces noise between bitlines and improve the performance and reliability, and reduce power consumption because the parasitic capacitances are reduced compared to a long metal bitline (i.e., where all the segments are connected together and operated as one).

Abstract: Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.

Abstract: A memory system (erg., memory card) for reading and programming (writing) of dual cell memory elements is disclosed. According to one aspect of the invention, all bit lines for the memory system can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

Abstract: Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.

Abstract: A memory system (erg., memory card) for reading and programming (writing) of dual cell memory elements is disclosed. According to one aspect of the invention, all bit lines for the memory system can be productively used during reading or programming so as to achieve improved (e.g., maximum) parallelism of read and/or program operations. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.