Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.