Abstract: Methods and systems for network devices are provided. One method includes receiving a serial data stream at a network interface of a network device coupled to a network link to communicate with other networked devices, the data stream including an alignment marker with a bit pattern for recovering a bit stream used by network device logic for processing the received serial data stream; using a plurality of comparators for simultaneously comparing within a single clock cycle, portions of a parallel data stream generated after converting the serial data stream by a de-serializer of the network device; detecting the bit pattern of the alignment marker in the parallel data stream by one of the plurality of comparators; storing a starting bit position of the alignment marker in the parallel data stream; and reordering the parallel data stream based on the stored starting bit position of the alignment marker.

Abstract: Methods and systems for network devices is provided. In one aspect, a network device includes a plurality of ports, where the plurality of ports are configured to operate in a first operating mode as a single port at a first speed and in a second operating mode where each of the plurality of ports operate as an independent port at a second operating speed; a shared memory device for staging information received from a network for the plurality of ports operating in the first operating mode and the second operating mode; a receive port selector that selects information from the shared memory device when the plurality of ports are operating in the second operating mode; and a shared error correction code module for decoding and performing error correction on information received via the network for the first operating mode and the second operating mode.

Abstract: A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Abstract: Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

Abstract: A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.

Abstract: A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Abstract: A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Abstract: A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

Abstract: A method whereby a fair port in a Fibre Channel Arbitrated Loop behaves unfairly during portions of its loop tenancy and behaves fairly during other portions. In a preferred implementation, the fair port establishes a first loop circuit with an initial destination port during a loop tenancy. Before relinquishing control of the loop to an arbitrating port, the fair port—under the control of a transfer protocol—establishes one or more subsequent loop circuits with other destination ports. Loop circuits are established in sequence without the fair port relinquishing control of the loop and rearbitrating. This continues until (1) the fair port establishes a loop circuit with every destination port to which it desires to exchange information; (2) a fixed time period has lapsed; and/or (3) a predefined maximum number of loop circuits are established.