Abstract: The various embodiments herein provide an energy efficient DC off-grid home system and a method for operating the same. The system generates, stores and delivers the solar energy to the connected equipments in a controlled and efficient manner. The system has several solar panels, a battery bank, a home control unit, several appliances and equipments which run on electric power and a remote terminal unit. The solar panels are used to capture maximum solar energy from the sun. The battery bank has several batteries arranged in series and parallel combinations to store maximum electrical energy. The home control unit is a central control station which assists in storing energy in the battery bank, delivering optimum energy to the electrical appliances and monitoring the healthy operating status of the entire system.

Abstract: The various embodiments herein provide an energy efficient DC off-grid home system and a method for operating the same. The system generates, stores and delivers the solar energy to the connected equipments in a controlled and efficient manner. The system has several solar panels, a battery bank, a home control unit, several appliances and equipments which run on electric power and a remote terminal unit. The solar panels are used to capture maximum solar energy from the sun. The battery bank has several batteries arranged in series and parallel combinations to store maximum electrical energy. The home control unit is a central control station which assists in storing energy in the battery bank, delivering optimum energy to the electrical appliances and monitoring the healthy operating status of the entire system.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating mode. When operating in the multi-level cell mode, the memory system stores multiple bits per cell. The memory system stores fewer bits per cell when operating in the reduced capacity. The transition between modes is achieved by setting all bits of a particular memory page to a specific value, for example, either a logic “1” or a logic “0.

Abstract: A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating mode. When operating in the multi-level cell mode, the memory system stores multiple bits per cell. The memory system stores fewer bits per cell when operating in the reduced capacity. The transition between modes is achieved by setting all bits of a particular memory page to a specific value, for example, either a logic “1” or a logic “0.

Abstract: A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

Abstract: A high-speed voltage level shifter. A transistor (10) may be connected to high voltage (VPP) and may act as a source of a limited current to a first node (21), and a driver (14, 15) connected to the first node may provide a level-shifted output signal (VOUT) to a memory control input line of a memory cell (6). A plurality of series-connected transistors (12A–12N) may be connected between a second node (22A) and a circuit ground, each transistor may have an input connected to a corresponding control signal (VIN-A to VIN-N) from a control circuit (5). A transistor (11) may be connected between the first node and the second node in a source-follower configuration and may have an input connected to a bias voltage (VBIAS) which may limit the voltage at node 22A, so transistors 12A–12N may be low-voltage, high speed transistors.

Abstract: An embodiment of the invention is directed to a method of operating a flash memory, which includes discharging at least one local wordline of an unselected block of flash memory cells during an interval in which a selected set of flash memory cells are being conditioned, such that the at least one local wordline does not develop a charge that is sufficient to corrupt the data stored in the unselected block.