Patents by Inventor Ravi Babu

Ravi Babu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11783106
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Patent number: 11768947
    Abstract: First data from a user device is received on an electronic computing device. The first data is encrypted to generate second data. The second data is fragmented and stored in a plurality of data stores.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: September 26, 2023
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Rameshchandra Bhaskar Ketharaju, Ravi Babu Bandla, Hem Shankar Karlapalem, Sarath Chava, Rama Rao Yadlapalli, Ajay Kumar Rentala, Vamsi Krishna Geda
  • Patent number: 11729371
    Abstract: Systems, methods, and computer-readable media are disclosed for improved camera color calibration. An example method may involve capturing a first wavelength emitted by a first type of traffic light. The example method may also involve determining, based on the first wavelength, a first color value associated with the wavelength emitted by the first type of traffic light. The example method may also involve capturing, by a first camera, a first image, video, or real-time feed of a first portion of a test target, the first portion of the test target including a first light color that is based on the first color value. The example method may also involve determining, based on the first image, video, or real-time feed of the first portion of a test target, a second color value output by the camera. The example method may also involve determining, based on a comparison between the first color value and the second color value, that a difference exists between the first color value and the second color value.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 15, 2023
    Assignee: Ford Global Technologies, LLC
    Inventors: Christopher N. St. John, Koji L. Gardiner, Ravi Babu Basavaraj, Bowei Zhang
  • Publication number: 20220116584
    Abstract: Systems, methods, and computer-readable media are disclosed for improved camera color calibration. An example method may involve capturing a first wavelength emitted by a first type of traffic light. The example method may also involve determining, based on the first wavelength, a first color value associated with the wavelength emitted by the first type of traffic light. The example method may also involve capturing, by a first camera, a first image, video, or real-time feed of a first portion of a test target, the first portion of the test target including a first light color that is based on the first color value. The example method may also involve determining, based on the first image, video, or real-time feed of the first portion of a test target, a second color value output by the camera. The example method may also involve determining, based on a comparison between the first color value and the second color value, that a difference exists between the first color value and the second color value.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Applicant: Argo AI, LLC
    Inventors: Christopher N. St. John, Koji L. Gardiner, Ravi Babu Basavaraj, Bowei Zhang
  • Patent number: 11126735
    Abstract: First data from a user device is received on an electronic computing device. The first data is encrypted to generate second data. The second data is fragmented and stored in a plurality of data stores.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Rameshchandra Bhaskar Ketharaju, Ravi Babu Bandla, Hem Shankar Karlapalem, Sarath Chava, Rama Rao Yadlapalli, Ajay Kumar Rentala, Vamsi Krishna Geda
  • Publication number: 20210236844
    Abstract: A phototherapy monitoring device (10) includes a housing (12) configured for attachment to a patient, and a user interfacing device. An optical bilimbin sensor (14) includes one or more light sources (16) operative to generate probe light and arranged on or in the housing such that the probe light is reflected from or transmitted through skin of the patient when the housing is attached to the patient; and one or more photodetectors (18) arranged on or in the housing to detect the probe light reflected from or transmitted through the skin of the patient. At least one electronic processor (28) is disposed on or in the housing and programmed to: continuously generate a current bilimbin level measurement from the detected probe light reflected from or transmitted through the skin of the patient; and control the user interfacing device to generate a notification when the current bilirubin level measurement satisfies a safe bilimbin level.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 5, 2021
    Inventors: ANSHUL JAIN, PRAVIN PAWAR, RAVINDRA BHAT, SHRUTIN ULMAN, RAVI BABU SUNDARAMOORYHY, NAGARAJU BUSSA
  • Publication number: 20210232743
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Ravi Babu PITTU, Chung-Hsing WANG, Sung-Yen YEH, Li Chung HSU
  • Patent number: 11003820
    Abstract: A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Patent number: 10977402
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20200372198
    Abstract: A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: RAVI BABU PITTU, LI-CHUNG HSU, SUNG-YEN YEH, CHUNG-HSING WANG
  • Publication number: 20200326223
    Abstract: The present invention relates to blood analysis. In order to determine the filling level of a cartridge, a device (10) is provided that comprises a cartridge interface (14) for receiving a cartridge and a liquid level sensor (16). A cartridge position guiding arrangement is configured to engage with the cartridge for providing a six degree-of-freedom constraint to the cartridge. The liquid level sensor comprises a light source (18) and a light detector (20). The light source is configured to provide a beam of light (22) incident upon a cavity surface (24) of an optical pit (26) of a cartridge received by the cartridge interface. The light detector is configured to detect a portion (28) of the beam of light reflected from the cavity surface of the optical pit. The device is configured to determine a filling level of the optical pit based on the detected portion of the beam of light.
    Type: Application
    Filed: May 17, 2017
    Publication date: October 15, 2020
    Inventors: Ravindra BHAT, Shashidharan ARPUTHA, Ravi Babu SUNDARAMOORYHY, Anil Shivram RAIKER, Anthonie VAN DER LUGT
  • Patent number: 10776545
    Abstract: A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Patent number: 10747924
    Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Publication number: 20200074030
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Ravi Babu PITTU, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Patent number: 10546138
    Abstract: First data from a user device is received on an electronic computing device. The first data is encrypted to generate second data. The second data is fragmented and stored in a plurality of data stores.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 28, 2020
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Rameshchandra Bhaskar Ketharaju, Ravi Babu Bandla, Hem Shankar Karlapalem, Sarath Chava, Rama Rao Yadlapalli, Ajay Kumar Rentala, Vamsi Krishna Geda
  • Publication number: 20200019663
    Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.
    Type: Application
    Filed: November 14, 2018
    Publication date: January 16, 2020
    Inventors: RAVI BABU PITTU, LI CHUNG HSU, SUNG-YEN YEH, CHUNG-HSING WANG
  • Patent number: 10503849
    Abstract: A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20190095562
    Abstract: A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: RAVI BABU PITTU, LI-CHUNG HSU, SUNG-YEN YEH, CHUNG-HSING WANG
  • Publication number: 20180173832
    Abstract: A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements.
    Type: Application
    Filed: September 13, 2017
    Publication date: June 21, 2018
    Inventors: Ravi Babu PITTU, Chung-Hsing WANG, Sung-Yen YEH, Li Chung HSU
  • Publication number: 20080015816
    Abstract: A system includes an analysis module and/or a prediction module. The analysis module receives data from a heat transfer device, and can compute a performance indicator indicative of an incipient anomaly condition of the heat transfer device based upon the received data, and/or can compute a normalized efficiency of the heat transfer device. The normalized efficiency represents a corrected efficiency that isolates effects of a process parameter on performance of the heat transfer device. The data represents a measurable process parameter or a change in a measurable process parameter in the heat transfer device. The prediction module receives the data and computes a performance indicator to predict performance degradation of the heat transfer device over time based upon the received data. Associated methods are provided.
    Type: Application
    Filed: September 28, 2007
    Publication date: January 17, 2008
    Applicant: General Electric Company
    Inventors: Vinay Jammu, Nishith Vora, Ravi Babu, Rama Mahajanam