Abstract: In one aspect, a highly scalable diffusion-couple apparatus includes a transfer chamber configured to load a wafer into a process chamber. The process chamber is configured to receive the wafer substrate from the transfer chamber. The process chamber comprises a chamber for growth of a diffusion material on the wafer. A heatable bottom substrate disk includes a first heating mechanism. The heatable bottom substrate disk is fixed and heatable to a specified temperature. The wafer is placed on the heatable bottom substrate disk. A heatable top substrate disk comprising a second heating mechanism. The heatable top substrate disk is configured to move up and down along an x axis and an x prime axis to apply a mechanical pressure to the wafer on the heatable bottom substrate disk. While the heatable top substrate disk applies the mechanical pressure a chamber pressure is maintained at a specified low value.

Abstract: In one aspect, a highly scalable diffusion-couple apparatus includes a transfer chamber configured to load a wafer into a process chamber. The process chamber is configured to receive the wafer substrate from the transfer chamber. The process chamber comprises a chamber for growth of a diffusion material on the wafer. A heatable bottom substrate disk includes a first heating mechanism. The heatable bottom substrate disk is fixed and heatable to a specified temperature. The wafer is placed on the heatable bottom substrate disk. A heatable top substrate disk comprising a second heating mechanism. The heatable top substrate disk is configured to move up and down along an x axis and an x prime axis to apply a mechanical pressure to the wafer on the heatable bottom substrate disk. While the heatable top substrate disk applies the mechanical pressure a chamber pressure is maintained at a specified low value.

Abstract: In one aspect, a highly scalable diffusion-couple apparatus includes a transfer chamber configured to load a wafer into a process chamber. The process chamber is configured to receive the wafer substrate from the transfer chamber. The process chamber comprises a chamber for growth of a diffusion material on the wafer. A heatable bottom substrate disk includes a first heating mechanism. The heatable bottom substrate disk is fixed and heatable to a specified temperature. The wafer is placed on the heatable bottom substrate disk. A heatable top substrate disk comprising a second heating mechanism. The heatable top substrate disk is configured to move up and down along an x axis and an x prime axis to apply a mechanical pressure to the wafer on the heatable bottom substrate disk. While the heatable top substrate disk applies the mechanical pressure a chamber pressure is maintained at a specified low value.

Abstract: A data processing method for a data processing system, comprising: initializing a value of a counter associated with a first entry to indicate a number of destinations of other entries on which the first entry depends; changing the value of the counter in a first direction in response to selecting a first one of the other entries; and changing the value of the counter in a second direction opposite the first direction in response to cancelling a second one of the other entries.

Abstract: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.

Abstract: A data processing method for a data processing system, comprising: initializing a value of a counter associated with a first entry to indicate a number of destinations of other entries on which the first entry depends; changing the value of the counter in a first direction in response to selecting a first one of the other entries; and changing the value of the counter in a second direction opposite the first direction in response to cancelling a second one of the other entries.

Abstract: Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a dynamic mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB.

Abstract: Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a static mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB.

Abstract: A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is canceled.

Abstract: A data processing system and method of clearing and rebuilding dependencies, the data processing method including changing a counter associated with a first entry in response to selecting a second entry; comparing the counter with a threshold; and indicating that the first entry is ready to be selected in response to comparing the counter with the threshold; wherein the first entry is dependent on the second entry.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.

Abstract: Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a static mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB.

Abstract: A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a source of the nested dependent instruction expire and a producer instruction speculatively waking up the dependent instruction is canceled.

Abstract: A data processing system and method of clearing and rebuilding dependencies, the data processing method including changing a counter associated with a first entry in response to selecting a second entry; comparing the counter with a threshold; and indicating that the first entry is ready to be selected in response to comparing the counter with the threshold; wherein the first entry is dependent on the second entry.

Abstract: Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a dynamic mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: The present invention is directed to methods of diagnosing Noonan-like syndrome with loose anagen hair comprising detecting a mutation in SHOC2 gene. One specific diagnostic mutation disclosed is an A-to-G transition at position 4 resulting in a mutation at position 2 of SHOC2 amino acid sequence from serine to glycine. The invention also provides related sequences and kits.

Abstract: The present invention is directed to methods of diagnosing Noonan-like syndrome with loose anagen hair comprising detecting a mutation in SHOC2 gene. One specific diagnostic mutation disclosed is an A-to-G transition at position 4 resulting in a mutation at position 2 of SHOC2 amino acid sequence from serine to glycine. The invention also provides related sequences and kits.

Abstract: The present invention relates to a family of graph-theory based methods for the analysis of intracellular signaling networks created from biomedical literature using data-mining processes or acquired through high-content experiments. The methods of the present invention can be used to identify functional dynamic modules within biological networks that can be analyzed quantitatively for input/output relationships. In particular, the present invention relates to a computer-aided method for the in-silico analysis of signaling and other cellular interaction pathways to rank drug targets, identify biomarkers, predict side effects, and classify/diagnose patients.