Patents by Inventor Ravi Jhota

Ravi Jhota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6492716
    Abstract: Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 10, 2002
    Assignee: ZeeVo, Inc.
    Inventors: Subhas Bothra, Thomas G. McKay, Ravi Jhota
  • Patent number: 5395773
    Abstract: After gates are patterned in a submicron CMOS process, a halo implant is performed with sufficient energy that the halo implant penetrates the gate structures to below the transistor channel regions. Where the substrate is not masked by gate materal, the halo implant penetrates below drain and source regions. During diffusion, this halo limits lateral diffusion of the source/drain dopants. The resulting transistor exhibits enhanced breakdown voltage characteristics during both on and off conditions.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: March 7, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: K. S. Ravindhran, Yu P. Han, Ravi Jhota, Walter D. Parmantie
  • Patent number: 5344787
    Abstract: The diffusion of P-type channel-stop implants into regions where P-type channels are to be formed which will connect N-type source and drain regions of a transistor element on a P-type substrate is effectively compensated for through angled implantation of an N-type dopant material into these regions. Angle implantation is performed by tilting and rotating the wafer in the presence of an N-type ion beam.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: September 6, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Samuel J. S. Nagalingam, Yu P. Han, Ravi Jhota