Patents by Inventor Ravi Jotwani

Ravi Jotwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374912
    Abstract: Methods and systems for performing exchange of data with third-party applications are described. The method includes receiving a request for performing document related operation on document using a third-party application. The method includes converting third-party application into containerized application using containerization mechanism. The method includes allocating virtual secured space to containerized application. The method includes encrypting document using public key of containerized application. The method includes providing encrypted document to containerized application that implements limitations on encrypted document. The method includes facilitating performance of document related operation on encrypted document to create updated document. The encrypted document is decrypted using private key of containerized application before performing document related operation on encrypted document.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: June 28, 2022
    Assignee: I2CHAIN, INC.
    Inventors: Mark Steven Manasse, Sanjay Jain, Ravi Jotwani, Ajay Jotwani
  • Publication number: 20220116404
    Abstract: Methods and systems for adaptive multi-factored geo-location based access rights management and enforcement for accessing location restricted data services are described. The method performed by server system includes receiving request to access a data service from a user device associated with a user. The method includes accessing geo-location information associated with the user upon receipt of request. The geo-location information includes geo-location data associated with the user device. The method includes generating geo-location signature associated with the user device, based on the geo-location information. The geo-location signature includes a plurality of location context identifiers. The method includes validating the user device when the geo-location signature and a geo-fence of the data service meet a matching threshold condition and transmitting a response message to the user device based on the validating step.
    Type: Application
    Filed: March 22, 2021
    Publication date: April 14, 2022
    Inventors: Mark Steven MANASSE, Sanjay JAIN, Ajay JOTWANI, Ananya JAIN, Patricia BOLTON, Ravi JOTWANI
  • Publication number: 20210218719
    Abstract: Methods and systems for performing exchange of data with third-party applications are described. The method includes receiving a request for performing document related operation on document using a third-party application. The method includes converting third-party application into containerized application using containerization mechanism. The method includes allocating virtual secured space to containerized application. The method includes encrypting document using public key of containerized application. The method includes providing encrypted document to containerized application that implements limitations on encrypted document. The method includes facilitating performance of document related operation on encrypted document to create updated document. The encrypted document is decrypted using private key of containerized application before performing document related operation on encrypted document.
    Type: Application
    Filed: December 7, 2020
    Publication date: July 15, 2021
    Inventors: Mark Steven MANASSE, Sanjay JAIN, Ravi JOTWANI, Ajay JOTWANI
  • Publication number: 20200090736
    Abstract: A write driver includes a first write data driver, a second write driver, and a control circuit. The first (second) write data driver provides a true (complement) write data signal to an output thereof at a high voltage when a true (complement) data signal is in a first logic state, at a ground voltage when the true (complement) data signal is in a second logic state and a negative bit line enable signal is inactive, and at a voltage below the ground voltage when the true (complement) data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold, and in an inactive state when the power supply voltage is above a second threshold higher than the first threshold.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alex Schaefer, Ravi Jotwani, David Hugh McIntyre
  • Patent number: 7977977
    Abstract: A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 12, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karthik Natarajan, Giridhar Narayanaswami, Spencer M. Gold, Stephen Kosonocky, Ravi Jotwani, Michael Braganza
  • Patent number: 6148381
    Abstract: A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: November 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ravi Jotwani