Patents by Inventor Ravi Jotwani

Ravi Jotwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7977977
    Abstract: A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 12, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karthik Natarajan, Giridhar Narayanaswami, Spencer M. Gold, Stephen Kosonocky, Ravi Jotwani, Michael Braganza
  • Patent number: 6148381
    Abstract: A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: November 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ravi Jotwani