Patents by Inventor Ravi K. Bonam
Ravi K. Bonam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887908Abstract: An electronic structure includes offset three-dimensional stacked chips; and a two-piece lid structure configured to extract heat from the bottom and top of the stacked chips.Type: GrantFiled: December 21, 2021Date of Patent: January 30, 2024Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, Katsuyuki Sakuma, Hilton T. Toy, Shidong Li, Ravi K Bonam
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Patent number: 11791270Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: GrantFiled: May 10, 2021Date of Patent: October 17, 2023Assignee: International Business Machines CorporationInventors: Kamal K Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, Ravi K. Bonam, Hiroyuki Mori, Yang Liu, Paul S. Andry, Isabel De Sousa
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Publication number: 20230197552Abstract: An electronic structure includes offset three-dimensional stacked chips; and a two-piece lid structure configured to extract heat from the bottom and top of the stacked chips.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Kamal K. Sikka, Katsuyuki Sakuma, Hilton T. Toy, Shidong Li, Ravi K. Bonam
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Publication number: 20230116390Abstract: The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.Type: ApplicationFiled: October 8, 2021Publication date: April 13, 2023Inventors: Scott David HALLE, Gauri KARVE, Effendi LEOBANDUNG, Gangadhara Raja MUTHINTI, Ravi K. BONAM
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Patent number: 11619877Abstract: A computer-implemented method for determining optical roughness in a semiconductor pattern structure that includes receiving, using a processor, optical responses spectra collected from the semiconductor pattern structure and constructing, using the processor optical critical dimension (OCD) models by using a set of input parameters for each layer of the semiconductor pattern structure. The method further includes calculating, using the processor, theoretical optical responses from a theoretical input generated by the OCD models. In addition, the method provides for comparing, using the processor, the optical responses spectra of the semiconductor pattern structure to the theoretical optical responses to determine output parameters for the optical roughness of the semiconductor pattern structure.Type: GrantFiled: July 22, 2022Date of Patent: April 4, 2023Assignee: International Business Machines CorporationInventors: Ravi K. Bonam, Gangadhara Raja Muthinti
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Publication number: 20220357648Abstract: A computer-implemented method for determining optical roughness in a semiconductor pattern structure that includes receiving, using a processor, optical responses spectra collected from the semiconductor pattern structure and constructing, using the processor optical critical dimension (OCD) models by using a set of input parameters for each layer of the semiconductor pattern structure. The method further includes calculating, using the processor, theoretical optical responses from a theoretical input generated by the OCD models. In addition, the method provides for comparing, using the processor, the optical responses spectra of the semiconductor pattern structure to the theoretical optical responses to determine output parameters for the optical roughness of the semiconductor pattern structure.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: RAVI K. BONAM, GANGADHARA RAJA MUTHINTI
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Publication number: 20220359401Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Kamal K. Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, RAVI K. BONAM, HIROYUKI MORI, Yang Liu, Paul S. Andry, Isabel De Sousa
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Patent number: 11480868Abstract: A computer-implemented method for determining optical roughness in a semiconductor pattern structure that includes receiving, using a processor, optical responses spectra collected from the semiconductor pattern structure and constructing, using the processor optical critical dimension (OCD) models by using a set of input parameters for each layer of the semiconductor pattern structure. The method further includes calculating, using the processor, theoretical optical responses from a theoretical input generated by the OCD models. In addition, the method provides for comparing, using the processor, the optical responses spectra of the semiconductor pattern structure to the theoretical optical responses to determine output parameters for the optical roughness of the semiconductor pattern structure.Type: GrantFiled: March 22, 2019Date of Patent: October 25, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ravi K. Bonam, Gangadhara Raja Muthinti
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Patent number: 11462512Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.Type: GrantFiled: December 28, 2020Date of Patent: October 4, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
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Patent number: 11239167Abstract: Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.Type: GrantFiled: December 4, 2019Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Mukta Ghate Farooq, Ravi K. Bonam, James J. Kelly, Spyridon Skordas
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Patent number: 11081424Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.Type: GrantFiled: June 18, 2019Date of Patent: August 3, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ravi K. Bonam, Kamal K. Sikka, Joshua M. Rubin, Iqbal Rashid Saraf, Fee Li Lie
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Patent number: 11049844Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.Type: GrantFiled: July 1, 2019Date of Patent: June 29, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James Kelly, Kamal K. Sikka, Joshua M. Rubin
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Publication number: 20210175174Abstract: Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.Type: ApplicationFiled: December 4, 2019Publication date: June 10, 2021Inventors: Mukta Ghate Farooq, Ravi K. Bonam, James J. Kelly, Spyridon Skordas
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Patent number: 10991635Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: GrantFiled: July 20, 2019Date of Patent: April 27, 2021Assignee: International Business Machines CorporationInventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Cournoyer
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Publication number: 20210118854Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
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Publication number: 20210091032Abstract: Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Inventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James J. Kelly
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Patent number: 10943883Abstract: Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.Type: GrantFiled: September 19, 2019Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James J. Kelly
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Patent number: 10937764Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.Type: GrantFiled: March 13, 2019Date of Patent: March 2, 2021Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
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Publication number: 20210020529Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.Type: ApplicationFiled: July 20, 2019Publication date: January 21, 2021Inventors: Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, Ramachandra Divakaruni, William J. Starke, Maryse Courmoyer
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Publication number: 20210005573Abstract: A semiconductor wafer includes a first substrate and a first etch stop layer formed on the first substrate. The etch stop layer has an opening. The semiconductor wafer further includes a second substrate and a second etch stop layer formed on the second substrate. The first substrate is bonded on top of the second substrate such that the first etch stop layer is positioned between the first substrate and the second substrate. A trench is formed in the opening.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Inventors: Ravi K. Bonam, Mukta Ghate Farooq, Dinesh Gupta, James Kelly, Kamal K. Sikka, JOSHUA M. RUBIN