Abstract: Embodiments described herein include a cascade Thermoelectric Module (TEM) that includes at least three headers. A first header and a first surface of a second header electrically connect first legs to form a stage of thermoelectric devices electrically connected in series, and define first and second leg placement positions for a subset of the first legs. A second surface of the second header and a third header electrically connect second legs to form another stage of thermoelectric devices electrically connected in series, and define first and second leg placement positions for a subset of the second legs. The stages are electrically coupled in series when the subsets of the first and second legs are positioned in their respective first leg placement positions, and the stages are electrically decoupled when the subsets of the first and second legs are positioned in their respective second leg placement positions.

Abstract: An electronic component package includes a RDL pattern comprising a redistribution pattern terminal. A buildup dielectric layer is formed on the RDL pattern, the buildup dielectric layer having a redistribution pattern terminal aperture exposing the redistribution pattern terminal. An interconnection ball is formed within the redistribution pattern terminal aperture and on the redistribution pattern terminal. The interconnection ball includes an enclosed portion having an outer concave surface within the buildup dielectric layer. The angle of intersection between the outer concave surface of the interconnection ball and the redistribution pattern is less than 90°. This minimizes stress between the interconnection ball and the redistribution pattern which, in turn, minimizes failure of the bond between the interconnection ball and the redistribution pattern.

Abstract: A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric layer opening and on the substrate terminal. A circuit pattern is plated on the first seed layer, wherein an exposed portion of the first seed layer is exposed from the circuit pattern. The exposed portion of the first seed layer is removed by laser-ablation. By using a laser-ablation process, a chemical etching process is avoided thus eliminating the need to treat or dispose of chemical etching hazardous waste. Further, circuit pattern width erosion and undercut of the circuit pattern associated with a chemical etching process are avoided.

Abstract: A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric layer opening and on the substrate terminal. A circuit pattern is plated on the first seed layer, wherein an exposed portion of the first seed layer is exposed from the circuit pattern. The exposed portion of the first seed layer is removed by laser-ablation. By using a laser-ablation process, a chemical etching process is avoided thus eliminating the need to treat or dispose of chemical etching hazardous waste. Further, circuit pattern width erosion and undercut of the circuit pattern associated with a chemical etching process are avoided.

Abstract: A method of fabricating a bumped chip package includes forming a first seed layer on a dielectric layer, the dielectric layer comprising a dielectric layer opening exposing a substrate terminal of a substrate, the first seed layer being formed within the dielectric layer opening and on the substrate terminal. A circuit pattern is plated on the first seed layer, wherein an exposed portion of the first seed layer is exposed from the circuit pattern. The exposed portion of the first seed layer is removed by laser-ablation. By using a laser-ablation process, a chemical etching process is avoided thus eliminating the need to treat or dispose of chemical etching hazardous waste. Further, circuit pattern width erosion and undercut of the circuit pattern associated with a chemical etching process are avoided.