Abstract: Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

Abstract: Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to an image signal processor architecture that may be optimized for low-power consumption, processing flexibility, and/or user experience are described. In an embodiment, an image signal processor may be partitioned into a plurality of partitions. Each partition may be capable of entering a lower power consumption state. Also, processing by each partition may be done in various modes to optimize for low-power consumption, processing flexibility, and/or user experience. Other embodiments are also disclosed and claimed.

Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.

Abstract: Apparatus, system, and method for scalable traceback techniques for channel decoding are described.

Abstract: A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the first latch, and a scan path to connect the output of the second latch to an input of a second save/restore cell of the save/restore chain. The apparatus is useful for fast context switching.

Abstract: A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.

Abstract: Apparatus, system, and method for scalable traceback techniques for channel decoding are described.

Abstract: In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.

Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.

Abstract: A memory addressing technique using load buffers-to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: A method and apparatus to compact trace in a trace buffer are described.

Abstract: A new branch notification processor instruction may be added to a pipelined processor with static branch prediction. The instruction may be used to instruct the processor to fetch the instruction at the branch's target.

Abstract: In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.

Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.