Abstract: In a phase-locked loop (PLL) frequency synthesizer, a first frequency divider divides an output signal from a voltage-controlled oscillator by a first divider value. A second frequency divider divides a reference signal by a second divider value. A charge pump increases a voltage level on a loop filter by injecting a charge pump current and decreases the voltage level on the loop filter by draining the charge pump current. A loop response control circuit adjusts the charge pump current. In particular, the first divider value may lie within one of a first plurality of ranges and/or the second divider value may lie within one of a second plurality of ranges. The charge pump current is adjusted based at least partially on which of the first plurality of ranges the first divider value lies within and/or which of the second plurality of ranges the second divider value lies within.