Patents by Inventor Ravi Kummaraguntla

Ravi Kummaraguntla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11621683
    Abstract: A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 4, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Wei Xu, Ravi Kummaraguntla, Paul Wilson, Mujo Kozak, Christian Larsen, John L. Melanson, Yongjie Cheng
  • Publication number: 20220247372
    Abstract: A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Wei XU, Ravi KUMMARAGUNTLA, Paul WILSON, Mujo KOZAK, Christian LARSEN, John L. MELANSON, Yongjie CHENG
  • Publication number: 20180324525
    Abstract: Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 8, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Vivek Saraf, Axel Thomsen, Ravi Kummaraguntla, John C. Tucker
  • Patent number: 10123117
    Abstract: Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 6, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Vivek Saraf, Axel Thomsen, Ravi Kummaraguntla, John C. Tucker
  • Patent number: 9490865
    Abstract: A transceiver includes a transmit/receive terminal, a receiver input terminal, a plurality of impedance transformation networks coupled in series, a plurality of power amplifiers, and a controller. Each impedance transformation network has first and second ports. The impedance transformation networks include at least one selectable impedance transformation network having a resonant mode and a termination mode. The power amplifiers have outputs respectively coupled to the second ports of corresponding ones of the impedance transformation networks. In a receive mode, the controller selects the resonant mode for each selectable impedance transformation network and disables all power amplifiers. In a transmit mode, the controller enables a selected power amplifier and selects the resonant mode of any upstream selectable impedance transformation network, and selects the termination mode of a downstream selectable impedance transformation network.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 8, 2016
    Assignee: SILICON LABORATORIES, INC
    Inventors: Aslamali A. Rafi, Ravi Kummaraguntla
  • Publication number: 20160233919
    Abstract: A transceiver includes a transmit/receive terminal, a receiver input terminal, a plurality of impedance transformation networks coupled in series, a plurality of power amplifiers, and a controller. Each impedance transformation network has first and second ports. The impedance transformation networks include at least one selectable impedance transformation network having a resonant mode and a termination mode. The power amplifiers have outputs respectively coupled to the second ports of corresponding ones of the impedance transformation networks. In a receive mode, the controller selects the resonant mode for each selectable impedance transformation network and disables all power amplifiers. In a transmit mode, the controller enables a selected power amplifier and selects the resonant mode of any upstream selectable impedance transformation network, and selects the termination mode of a downstream selectable impedance transformation network.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Applicant: Silicon Laboratories Inc.
    Inventors: Aslamali A. Rafi, Ravi Kummaraguntla
  • Publication number: 20160156380
    Abstract: A transceiver comprises a transmit/receive terminal, a receiver input terminal, a scalable impedance network, a plurality of power amplifiers, and a receiver. The scalable impedance network is coupled between the transmit/receive terminal and the receiver input terminal and has a plurality of taps in an order between the transmit/receive terminal and the receiver input terminal, in which an impedance looking into any given tap toward the transmit/receive terminal is smaller than an impedance looking into a subsequent tap toward the transmit/receive terminal, if any, in the order. The plurality of power amplifiers are arranged in an order and have outputs respectively coupled to the plurality of taps of the scalable impedance network. A power of any given power amplifier is higher than a power of a subsequent power amplifier, if any, in the order. The receiver is coupled to the receiver input terminal.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 2, 2016
    Applicant: SILICON LABORATORIES INC.
    Inventors: Aslamali A. Rafi, Ravi Kummaraguntla
  • Patent number: 9350412
    Abstract: A transceiver comprises a transmit/receive terminal, a receiver input terminal, a scalable impedance network, a plurality of power amplifiers, and a receiver. The scalable impedance network is coupled between the transmit/receive terminal and the receiver input terminal and has a plurality of taps in an order between the transmit/receive terminal and the receiver input terminal, in which an impedance looking into any given tap toward the transmit/receive terminal is smaller than an impedance looking into a subsequent tap toward the transmit/receive terminal, if any, in the order. The plurality of power amplifiers are arranged in an order and have outputs respectively coupled to the plurality of taps of the scalable impedance network. A power of any given power amplifier is higher than a power of a subsequent power amplifier, if any, in the order. The receiver is coupled to the receiver input terminal.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 24, 2016
    Assignee: SILICON LABORATORIES INC.
    Inventors: Aslamali A. Rafi, Ravi Kummaraguntla
  • Patent number: 8604884
    Abstract: A ring oscillator that is more insensitive to power supply ripple utilizes an amplifier circuit having a first input coupled to a reference voltage. A current is generated that represents a control voltage supplied to the oscillator control circuit. That current is mirrored and supplied as a control current to the oscillator. An amplifier is used in a feedback loop to ensure that incremental variations in source to drain voltage of a first transistor of the current mirror is present in a second transistor of the current mirror to make the control current more immune to supply ripple.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Abdulkerim L. Coban, Ravi Kummaraguntla
  • Publication number: 20130002361
    Abstract: A ring oscillator that is more insensitive to power supply ripple utilizes an amplifier circuit having a first input coupled to a reference voltage. A current is generated that represents a control voltage supplied to the oscillator control circuit. That current is mirrored and supplied as a control current to the oscillator. An amplifier is used in a feedback loop to ensure that incremental variations in source to drain voltage of a first transistor of the current mirror is present in a second transistor of the current mirror to make the control current more immune to supply ripple.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Abdulkerim L. Coban, Ravi Kummaraguntla