Patents by Inventor Ravi Lakshmipathy

Ravi Lakshmipathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optimized synchronous scan flip flop circuit
    Patent number: 8990648
    Abstract: According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ravi Lakshmipathy, Balaji Upputuri
  • OPTIMIZED SYNCHRONOUS SCAN FLIP FLOP CIRCUIT
    Publication number: 20130262943
    Abstract: According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: RAVI LAKSHMIPATHY, BALAJI UPPUTURI
  • Structure for window comparator circuit for clock data recovery from bipolar RZ data
    Patent number: 8477896
    Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Santoshkumar Jinagar, Animesh Khare, Ravi Lakshmipathy, Narendra K. Rane, Umesh Shukla, Pradeep K. Vanama
  • DESIGN STRUCTURE FOR WINDOW COMPARATOR CIRCUIT FOR CLOCK DATA RECOVERY FROM BIPOLAR RZ DATA
    Publication number: 20120170698
    Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Santoshkumar Jinagar, Animesh Khare, Ravi Lakshmipathy, Narendra K. Rane, Umesh Shukla, Pradeep K. Vanama