Patents by Inventor Ravi Mahajan

Ravi Mahajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941245
    Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Oswald Skeete, Ravi Mahajan, John Guzek
  • Patent number: 8441809
    Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Mahajan, Sandeep Sane
  • Patent number: 8064224
    Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Mahajan, Sandeep Sane
  • Publication number: 20110281375
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Inventors: Rajasekaran Swaminathan, Ravindranath Ravi Mahajan, John S. Guzek
  • Publication number: 20110241208
    Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Inventors: Ravi Mahajan, Sandeep Sane
  • Publication number: 20110101491
    Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.
    Type: Application
    Filed: September 25, 2007
    Publication date: May 5, 2011
    Inventors: OSWALD SKEETE, RAVI MAHAJAN, JOHN GUZEK
  • Patent number: 7764499
    Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the pipe.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: July 27, 2010
    Assignee: Intel Corporation
    Inventors: Ioan Sauciuc, Ravi Mahajan
  • Publication number: 20090244874
    Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Ravi Mahajan, Sandeep Sane
  • Publication number: 20090237884
    Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the pipe.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 24, 2009
    Applicant: Intel Corporation
    Inventors: loan Sauciuc, Ravi Mahajan
  • Patent number: 7576432
    Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, James G. Maveety, Alan M. Myers, Quat T. Vu, Ravi Prasher, Ravi Mahajan, Gilroy Vandentop
  • Patent number: 7539016
    Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the pipe.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Ioan Sauciuc, Ravi Mahajan
  • Publication number: 20090084931
    Abstract: A liquid cooling device for a die including a support block supporting a plurality of substantially vertical channels transporting fluid to and from a bare die surface for heat removal. The device is mounted on top of a bare die using a frame or spring. In another embodiment, the device allows thermoelectric cooling of a dedicated fluid line.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Ioan Sauciuc, Gregory M. Chrysler, Ravi Mahajan
  • Publication number: 20070164427
    Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a heat pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the heat pipe.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 19, 2007
    Inventors: Ioan Sauciuc, Ravi Mahajan
  • Publication number: 20060139883
    Abstract: To accommodate high power densities associated with high-performance integrated circuits, an integrated circuit (IC) package includes a heat-dissipating structure in which heat is dissipated from a surface of one or more dice to a heat spreader. The heat spreader has a fluid-conducting channel formed therein, and a fluid coolant may be circulated through the channel via a micropump. In an embodiment, the channel is located at or near a surface of the heat spreader, and a heat-generating IC is in thermal contact with the heat spreader. In an embodiment, the IC is a thinned die that is coupled to the heat spreader via a thinned thermal interface material. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Application
    Filed: February 27, 2006
    Publication date: June 29, 2006
    Inventors: Chuan Hu, Ravi Mahajan
  • Publication number: 20060127672
    Abstract: A method of preparing a diamond body, and a diamond body thus prepared. A covering layer is provided on at least one surface of the diamond body such that the covering layer adheres to the at least one surface. The covering layer is in turn provided with a predetermined configuration.
    Type: Application
    Filed: February 15, 2006
    Publication date: June 15, 2006
    Inventors: Gregory Chrysler, Abhay Watwe, Ravi Mahajan
  • Publication number: 20060055030
    Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 16, 2006
    Inventors: Sarah Kim, R. List, James Maveety, Alan Myers, Quat Vu, Ravi Prasher, Ravi Mahajan, Gilroy Vandentop
  • Patent number: 6992381
    Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, James G. Maveety, Alan M. Myers, Quat T. Vu, Ravi Prasher, Ravi Mahajan, Gilroy Vandentop
  • Patent number: 6934154
    Abstract: Two-phase microchannel heat exchangers for cooling integrated circuit (IC) dies and cooling systems employing the same are disclosed. The heat exchangers include thermal masses having a plurality of microchannels formed therein. In one set of configurations, the IC die is coupled to a thermal mass having a plurality of open microchannels such that a hermetic seal is formed between the die and the bases of the microchannel walls, thus forming a plurality of closed microchannels. In another set of configurations, a separate microchannel heat exchanger is thermally coupled to an IC die and operatively coupled to the IC die via coupling to a substrate on which the IC die is mounted. The microchannel heat exchangers may be employed in a closed loop cooling system includes a pump and a heat rejecter. The microchannels are configured to support two-phase heat transfer using a working fluid such as water.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventors: Ravi Prasher, Ravi Mahajan
  • Patent number: 6903929
    Abstract: Integrated circuit (IC) packages employing two-phase microchannel heat exchangers for cooling the packages' IC dies and cooling systems employing the same are disclosed. The heat exchangers include thermal masses having a plurality of microchannels formed therein. In one set of configurations, the IC die is thermally coupled to a pair of microchannel heat exchangers disposed on opposite sides of the die. Top-side microchannel heat exchangers include a thermal mass having a plurality of open microchannels having wall bases that are hermetically sealed with the top surface of the die, thus forming a plurality of closed microchannels. Alternatively, a separate microchannel heat exchanger is thermally coupled to an IC die and operatively coupled to the IC die via coupling to a substrate on which the IC die is mounted. Bottom-side heat exchangers include substrates and chip carriers having microchannels formed therethrough that are thermally coupled to the IC die.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventors: Ravi Prasher, Ravi Mahajan
  • Publication number: 20050117299
    Abstract: A channeled heat sink and a device chassis having one or more integral condensing volumes suited for heat rejecters in conduction with two-phase cooling loops. The channeled heat sink includes a base from which a plurality of hollowed fins extend. Each hollowed fin defines an internal channel having walls configured to condense a working fluid from a vapor phase upon entering the channel into a liquid phase upon exiting the channel. The chassis comprises a shell formed from a base coupled to a plurality of walls. At least one condensing volume is formed in the base and/or the walls of the chassis. The condensing volume is configured to condense a working fluid from a vapor phase to a liquid phase as the working fluid is passed through it.
    Type: Application
    Filed: January 3, 2005
    Publication date: June 2, 2005
    Inventors: Ravi Prasher, Ravi Mahajan