Abstract: A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

Abstract: A fracking device (100) for generating shock waves in a well bore (102) comprises a fracking gun (110). The fracking gun (110) includes a cartridge (200) having a hollow cavity and a cylinder (202) disposed inside the hollow cavity of the cartridge (200). The cylinder (202) has a first chamber (210) and a second chamber (212). The first chamber (210) includes a plurality of explosive charges (206) positioned on an inner surface of the cylinder (202), wherein each of the explosive charges (206) contains an explosive mixture comprising hydrogen and stoichiometric oxygen in a predetermined ratio. The second chamber (212) contains a combustion-neutral gas. The first chamber (210) is separated from the second chamber (212) by a diaphragm (214).

Abstract: A solvent-free solid electrolyte is provided for an alkali metal solid state battery including an alkali metal conducting salt and a semi-interpenetrating network (sIPN) of a crosslinked and a non-crosslinked polymer. The semi-interpenetrating network is selected from a non-crosslinked polymer selected from the group consisting of polyethylene oxide (PEO), polycarbonate (PC), polycaprolactone (PCL), chain end modified derivatives of these polymers or mixtures of at least two components thereof, and the crosslinked polymer comprises polyethylene glycol dimethacrylate (PEGdMA). Furthermore, to a process is provided for preparing a solid electrolyte and to an alkali metal battery including the solid electrolyte.

Abstract: A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

Abstract: A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.

Abstract: Techniques for refinement of data pipelines are provided. An original file of serialized objects is received, and an original pipeline comprising a plurality of transformations is identified based on the original file. A first computing cost is determined for a first transformation of the plurality of transformations. The first transformation is modified using a predefined optimization, and a second cost of the modified first transformation is determined. Upon determining that the second cost is lower than the first cost, the first transformation is replaced, in the original pipeline, with the optimized first transformation.

Abstract: A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

Abstract: A measuring arrangement for secondary alkaline solid electrolyte batteries comprising—two electrically non-conductive cell body halves, both cell body halves comprising at least one and one cell body half comprising at least three feedthroughs, both cell body halves forming a receiving space for receiving a solid electrolyte battery cell comprising at least an anode, a cathode and a solid electrolyte. An electrically conductive holding element for each feedthrough; an electrical contact element for each support element, the electrical contact element being adapted to change its length in response to the force applied to the element; and two planar current conductors comprising electrically conductive and electrically non-conductive regions, at least one of the current conductors being adapted to form at least three separate electrically conductive connections between the contact elements and an electrode of the solid electrolyte battery cell.

Abstract: A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.

Abstract: A memory network can be constructed with at least memory write weightings, memory read weightings and at least one read vector, the memory write weightings parameterizing memory write operations of a neural network to the memory matrix, the memory read weightings parameterizing memory read operations of the neural network from the memory matrix. At least one of the write weightings, the read weightings, or elements of the at least one read vector, can be initialized to have sparsity and/or low discrepancy sampling pattern. The memory network can be trained to perform a task.

Abstract: The present invention relates to a curable composition for preparing a composite polymer electrode, the curable composition containing: A) a Li-ion conducting solid electrolyte whose general composition has the formula: Li7+x?yMIIxMIII3?xMIV2?yO12 wherein MII, MIII, MIV, MV are species of valence II to V; where 0?x<3, preferably 0?x?2; and 0?y<2 preferably 0?y?1; (B) a polymer; (C) a lithium salt; (D) an active plasticizer; and (E) a photoinitiator. The invention also relates to a process of preparing the curable composition, cured compositions and films derived from the curable composition, and solid-state lithium batteries whose solid electrolyte layer contains a cured composition or a cured film according to the invention.

Abstract: A fracking device (100) for generating shock waves in a well bore (102) comprises a fracking gun (110). The fracking gun (110) includes a cartridge (200) having a hollow cavity and a cylinder (202) disposed inside the hollow cavity of the cartridge (200). The cylinder (202) has a first chamber (210) and a second chamber (212). The first chamber (210) includes a plurality of explosive charges (206) positioned on an inner surface of the cylinder (202), wherein each of the explosive charges (206) contains an explosive mixture comprising hydrogen and stoichiometric oxygen in a predetermined ratio. The second chamber (212) contains a combustion-neutral gas. The first chamber (210) is separated from the second chamber (212) by a diaphragm (214).

Abstract: A method of text classification includes generating a text embedding vector representing a text sample and applying weights of a regression layer to the text embedding vector to generate a first data model output vector. The method also includes generating a plurality of prototype embedding vectors associated with a respective classification labels and comparing the plurality of prototype embedding vectors to the text embedding vector to generate a second data model output vector. The method further includes assigning a particular classification label to the text sample based on the first data model output vector, the second data model output vector, and one or more weighting values.

Abstract: An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.

Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Abstract: Application of multi-task learning technique(s) to machine logic (for example, software) used to detect financial transactions that are fraudulent or at least considered likely to be fraudulent. Some embodiments include adjustments and/or additions to conventional multi-task learning techniques in order to make the multi-task learning techniques more suitable for use in fraud detection software. One example of this is compensation for class imbalances that are to be expected as between the likely-fraud and not-likely-fraud classes of data sets (for example, training data sets, runtime data sets).

Abstract: Techniques for refinement of data pipelines are provided. An original file of serialized objects is received, and an original pipeline comprising a plurality of transformations is identified based on the original file. A first computing cost is determined for a first transformation of the plurality of transformations. The first transformation is modified using a predefined optimization, and a second cost of the modified first transformation is determined. Upon determining that the second cost is lower than the first cost, the first transformation is replaced, in the original pipeline, with the optimized first transformation.

Abstract: A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

Abstract: An approach is disclosed that relocates a named data element. A request to move a name corresponding to the named data element is received from a first storage area in a Coordination Namespace to a second storage area in the Coordination Namespace. The first storage area has a first level of persistence, and the second storage area has a second level of persistence. The named data element exists in a Coordination Namespace that is allocated in a memory distributed amongst a plurality of nodes that include the local node and one or more remote nodes. The approach then creates a copy of the named data element in the second storage area.

Abstract: Embodiments for mitigating cache-based data security vulnerabilities in a computing environment are provided. Cache pollution due to speculative memory accesses within a speculative path is avoided by delaying data updates to a cache and memory subsystem until the speculative memory accesses are resolved. A speculative buffer is used to maintain the speculative memory accesses such that a state of the cache remains unchanged until the speculative memory accesses are committed.