Patents by Inventor Ravi P. Annavajjhala

Ravi P. Annavajjhala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6917554
    Abstract: A protection circuit that permits the use of thin oxide transistor devices. In one embodiment, the circuit is used to protect internal nodes of a flash EEPROM chip from a power pad voltage. A thin oxide device can be used to directly couple the power pad to an internal node of the flash chip. Optionally, thin oxide devices can also be used to set the steady state internal node voltage and a current source can be coupled to the node to bleed sub-threshold current. In yet another embodiment, a pull down circuit is coupled to the node to pull the node immediately down to a desired steady state voltage when the EEPROM algorithm is completed.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: July 12, 2005
    Assignee: Intel Corporation
    Inventor: Ravi P. Annavajjhala
  • Patent number: 6836176
    Abstract: A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 28, 2004
    Assignee: Intel Corporation
    Inventors: Raymond W. Zeng, Ravi P. Annavajjhala, Mary Frances Therese B. Yuvienco
  • Publication number: 20040223375
    Abstract: A protection circuit that permits the use of thin oxide transistor devices. In one embodiment, the circuit is used to protect internal nodes of a flash EEPROM chip from a power pad voltage. A thin oxide device can be used to directly couple the power pad to an internal node of the flash chip. Optionally, thin oxide devices can also be used to set the steady state internal node voltage and a current source can be coupled to the node to bleed sub-threshold current. In yet another embodiment, a pull down circuit is coupled to the node to pull the node immediately down to a desired steady state voltage when the EEPROM algorithm is completed.
    Type: Application
    Filed: July 24, 2003
    Publication date: November 11, 2004
    Applicant: Intel Corporation, a Delaware corporation
    Inventor: Ravi P. Annavajjhala
  • Patent number: 6605984
    Abstract: Circuits reduce the ripple in charge pump output by staggering the times at which charge is drawn from the pump. In one embodiment, the outputs of a two-array high current pump are staggered by multiplexing two pairs of clock inputs, the second pair being 180 degrees out of phase with the first clock input pair. When an EEPROM is in a programming or erase algorithm, multiplexers switch the clock inputs to the second array, effectively inverting the input clock signals. After switching, the output from the second array is 180 degrees out of phase with the output from the first array. The peak-to-peak ripple in the charge pump output is thereby reduced to about 400 mV or less.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Ravi P. Annavajjhala, Mary Frances Therese B. Yuvienco
  • Publication number: 20030122610
    Abstract: A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.
    Type: Application
    Filed: June 27, 2002
    Publication date: July 3, 2003
    Inventors: Raymond W. Zeng, Ravi P. Annavajjhala, Mary Frances Therese B. Yuvienco
  • Publication number: 20030122609
    Abstract: Circuits that reduce the ripple in charge pump output by staggering the times at which charge is drawn from the pump. In one embodiment, the outputs a two-array high current pump are staggered by multiplexing two pairs of clock inputs, the second pair being 180 degrees out phase with the first clock input pair. When the EEPROM is in a programming or erase algorithm, multiplexers switch the clock inputs to the second array, effectively inverting the input clock signals. After switching, the output from the second array is 180 degrees out of phase with the output from the first array. The peak-to-peak ripple in the charge pump output is thereby reduced to about 400 mV or less.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventors: Ravi P. Annavajjhala, Mary Frances Therese B. Yuvienco
  • Publication number: 20030123299
    Abstract: A protection circuit that permits the use of thin oxide transistor devices. In one embodiment, the circuit is used to protect internal nodes of a flash EEPROM chip from a power pad voltage. A thin oxide device can be used to directly couple the power pad to an internal node of the flash chip. Optionally, thin oxide devices can also be used to set the steady state internal node voltage and a current source can be coupled to the node to bleed sub-threshold current. In yet another embodiment, a pull down circuit is coupled to the node to pull the node immediately down to a desired steady state voltage when the EEPROM algorithm is completed.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventor: Ravi P. Annavajjhala