Patents by Inventor Ravi P. Srivastava

Ravi P. Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005454
    Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Inventors: Hsueh-Chung CHEN, Ravi P. SRIVASTAVA, Somnath GHOSH, Nicholas V. LICAUSI, Terry A. SPOONER, Sean REIDY
  • Patent number: 10818494
    Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Ravi P. Srivastava, Somnath Ghosh, Nicholas V. Licausi, Terry A. Spooner, Sean Reidy
  • Patent number: 10818557
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Patent number: 10714380
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sipeng Gu, Sunil K. Singh, Xinyuan Dou, Akshey Sehgal, Zhiguo Sun
  • Publication number: 20200135545
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Ravi P. SRIVASTAVA, Sipeng GU, Sunil K. SINGH, Xinyuan DOU, Akshey SEHGAL, Zhiguo SUN
  • Publication number: 20200083043
    Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Inventors: Hsueh-Chung CHEN, Ravi P. SRIVASTAVA, Somnath GHOSH, Nicholas V. LICAUSI, Terry A. SPOONER, Sean REIDY
  • Publication number: 20200013678
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
  • Patent number: 10504774
    Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Sohan S. Mehta, Sherjang Singh, Ravi P. Srivastava
  • Patent number: 10395941
    Abstract: A self-aligned double patterning (SADP) method is disclosed. The method may include forming a mandrel over an underlying layer, and undercutting the mandrel forming an undercut space under opposing sides of the mandrel. A pair of spacers may be formed adjacent the mandrel, each spacer including a vertical spacer portion on each side of the mandrel and an undercut spacer portion extending into the undercut space from the vertical spacer portion, the undercut spacer portions defining a sub-lithographic lateral dimension therebetween. The mandrels may be removed and, a sub-lithographic feature etched into at least the underlying layer using the spacers.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Hsueh-Chung Chen
  • Patent number: 10347528
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Sipeng Gu, Akshey Sehgal
  • Patent number: 10312188
    Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi P. Srivastava, Sunil K. Singh
  • Publication number: 20180025936
    Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.
    Type: Application
    Filed: July 20, 2016
    Publication date: January 25, 2018
    Inventors: Sunil K. Singh, Sohan S. Mehta, Sherjang Singh, Ravi P. Srivastava
  • Publication number: 20170025347
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Application
    Filed: February 12, 2016
    Publication date: January 26, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 9293363
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Publication number: 20150332959
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 19, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 9117822
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 25, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 8183149
    Abstract: A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: May 22, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: David M. Permana, Ravi P. Srivastava, Haifeng Sheng, Dimitri R. Kioussis