Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: Interconnect structures and methods for forming an interconnect structure. A dielectric layer of a metallization level is deposited and a trench is patterned in the dielectric layer. A sacrificial layer is formed in the trench in the dielectric layer. The sacrificial layer is patterned to form a first trench and a second trench separated from the first trench by a section of the sacrificial layer. A first metal interconnect is formed in the first trench, a second metal interconnect is formed in the second trench, and a porous cap layer is formed over the first metal interconnect, the second metal interconnect, and the section of the sacrificial layer. After forming the porous cap layer, the section of the sacrificial layer is removed.

Abstract: The disclosure is directed to a method for lithographic patterning. The method may include: exposing a photoresist to a radiant energy; developing the photoresist in a first developer, thereby creating an opening within the photoresist including sidewalls having a slant; and developing the photoresist in a second developer immediately after the developing of the photoresist in the first developer, thereby reducing the slant of the sidewalls of the opening. Where the photoresist is a positive tone development (PTD) photoresist, the first developer may include a positive developer, and the second developer may include a negative developer. Where the photoresist is a negative tone development (NTD) photoresist, the first developer may include a negative developer, and the second developer may include a positive developer.

Abstract: Methods of self-aligned double patterning and improved interconnect structures formed by self-aligned double patterning. A mandrel line including an upper layer and a lower layer is formed over a hardmask. A non-mandrel cut block is formed over a portion of a non-mandrel line, after which the upper layer of the mandrel line is removed. An etch mask is formed over a first section of the lower layer of the mandrel line defining a mandrel cut block over a first portion of the hardmask. The first section of the lower layer is arranged between adjacent second sections of the lower layer. The second sections of the lower layer of the mandrel line are removed to expose respective second portions of the hardmask, and the second portions of the hardmask are removed to form a trench. The mandrel cut block masks the first portion of the hardmask during the etching process.

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.