Abstract: The present invention relates to methods and systems for obtaining a plantlet from a plurality of somatic plant embryos, and to the use of a compressible and resilient solid substrate comprising a plurality of hydrophilic and biodegradable polymer fibres, as a germination substrate in a method for germination of a somatic plant embryo.

Abstract: Embodiments herein disclose methods for handling a data driven model in a wireless communication network. The method includes identifying, by a first electronic device, a common data driven model capability between a capability information of one or more first data driven model and a capability information of one or more second data driven model. The one or more first data driven model is associated with the first electronic device and the one or more second data driven model is associated with the second electronic device. Further, the method includes performing, by the first electronic device, one of: storing the common data driven model capability in the first electronic device on identifying the common data driven model capability, and disabling a data driven model capability in the first electronic device on not identifying the common data driven model capability.

Abstract: A lyophilized pharmaceutical composition of hydrolytically unstable pharmaceutical compounds, such as phenobarbital or salts thereof, is provided. An aqueous solution for injection of phenobarbital or salts thereof that is reconstituted from the lyophilized pharmaceutical composition is provided. The pharmaceutical compositions of the present disclosure have an ethanol content in the range from about 5000 ppm to about 70000 ppm. The composition of the present disclosure, in certain embodiments, is stable following two years of storage, wherein the total impurities do not exceed 0.5%. The pharmaceutical compositions of the present disclosure may be used for the treatment of neonatal seizures.

Abstract: Methods and apparatus are provided for testing computing devices. A host computing device is provided for testing devices under test (DUTs) using a test suite that includes first and second tests. The DUTs can include a first group of DUTs with a first DUT and a second group of DUTs with a second DUT. The first and second groups of DUTs can share a common design. The host computing device can determine that the DUTs execute the first test before the second test. The host computing device can receive failing first test results for the first DUT. The host computing device can determine, based on the first test results and that the first and second DUT groups share a common design, to execute the second test before the first test and can subsequently instruct the second DUT to execute the second test before the first test.

Abstract: Methods and apparatus are provided for testing computing devices. A host computing device is provided for testing devices under test (DUTs) using a test suite that includes first and second tests. The DUTs can include a first group of DUTs with a first DUT and a second group of DUTs with a second DUT. The first and second groups of DUTs can share a common design. The host computing device can determine that the DUTs execute the first test before the second test. The host computing device can receive failing first test results for the first DUT. The host computing device can determine, based on the first test results and that the first and second DUT groups share a common design, to execute the second test before the first test and can subsequently instruct the second DUT to execute the second test before the first test.

Abstract: A method, system and computer program product for preserving event data for lazily-loaded macro components. Upon detecting an event published by a publisher, the logical channel of the detected event is identified. If one of the macro components to be lazily-loaded is a primary receiver for that logical channel (determined by performing a table-lookup of a data structure containing a listing of macro components and their associated logical channels for which they are to be the primary receivers), then the indication of the logical channel of the detected event along with the data of the published event are stored as a key/value pair in a data structure. Upon the macro component to be lazily-loaded having been loaded, the data of the published event associated with the logical channel for which the loaded macro component is a primary receiver is retrieved and transmitted to that logical channel.

Abstract: A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code (“code unit”) and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit.

Abstract: Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task.

Abstract: A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code (“code unit”) and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit.

Abstract: A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code (“code unit”) and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit.

Abstract: A method, system and computer program product for updating the display state of the user interface of a subscriber client. A macro component definition file is inspected to obtain the listing of events associated with each macro component listed in the macro component definition file. An event callback function is created for each macro component listed in the macro component definition file, where the callback function will update the displayed user interface of the subscriber client to be the display state of the macro component when one its associated events is published by the publisher. Upon detecting a published event, the event callback function associated with the published event is executed thereby automatically updating the display state of the user interface of the subscriber client to be the display state of the macro component associated with the published event.

Abstract: A method, system and computer program product for preserving event data for lazily-loaded macro components. Upon detecting an event published by a publisher, the logical channel of the detected event is identified. If one of the macro components to be lazily-loaded is a primary receiver for that logical channel (determined by performing a table-lookup of a data structure containing a listing of macro components and their associated logical channels for which they are to be the primary receivers), then the indication of the logical channel of the detected event along with the data of the published event are stored as a key/value pair in a data structure. Upon the macro component to be lazily-loaded having been loaded, the data of the published event associated with the logical channel for which the loaded macro component is a primary receiver is retrieved and transmitted to that logical channel.

Abstract: A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code (“code unit”) and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit.

Abstract: Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task.

Abstract: A secondary cache control system for a computer system is disclosed. The system is utilized advantageously to reduce the cost of the SRAM while not degrading the overall performance of the CPU associated with the computer. The system latches the data from the CPU until the CPU hits a "dead time". When this dead time occurs, the data is written into the SRAM. By writing to the SRAM at this time the performance of the computer system is not degraded and the cost of the SRAM is significantly reduced.