Patents by Inventor Ravi Shekhar

Ravi Shekhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8923277
    Abstract: In some embodiments, a switch fabric system includes a compute device to communicate with a network control entity at an access switch from a set of access switches that are coupled to each other via a switch fabric. The compute device stores a map between a physical identifier of a port of the access switch and both a logical identifier of the network control entity and a logical identifier of the port. The compute device can forward to the network control entity, based on the map, configuration information that references the port by the logical identifier of the port.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: December 30, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Ravi Shekhar, Quaizar Vohra
  • Patent number: 8903942
    Abstract: In some embodiments, a system includes a first network control entity, a second network control entity and a third network control entity. The first network control entity and the second network control entity are associated with a first network segment. The third network control entity is associated with a second network segment. The first network control entity is operable to send to the second network control entity an identifier of the first network segment and forwarding-state information associated with a data port at a first network element. The second network control entity is operable to receive the identifier of the first network segment and the forwarding-state information. The second network control entity is operable to send the forwarding-state information to a second network element. The first network control entity does not send the identifier of the first network segment and the forwarding-state information to the third network control entity.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: December 2, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Vijayabhaskar Annamalai Kalusivalingam, Jaihari Loganathan, Ravi Shekhar, Jeelani Syed, Quaizar Vohra
  • Patent number: 8891406
    Abstract: A system includes multiple edge devices configured to be operatively coupled to a switch fabric. The switch fabric and the multiple edge devices collectively define at least a portion of a core portion of a data center. An edge device from the multiple edge devices is configured to receive a physical address value included in a request from a source peripheral processing device disposed outside of the core portion of the data center. The physical address value represents a destination of a packet queued at the source peripheral processing device. The edge device is configured to send, in response to the request, a tunnel value representing a physical address space including the physical address value to the source peripheral processing device.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 18, 2014
    Assignee: Juniper Networks, Inc.
    Inventor: Ravi Shekhar
  • Publication number: 20140333460
    Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.
    Type: Application
    Filed: July 29, 2014
    Publication date: November 13, 2014
    Applicant: STMicroelectronics International N.V.
    Inventors: Ravindranath Ramalingaiah Munnan, Raghu Ravindran, Ravi Shekhar
  • Patent number: 8803716
    Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Ravindranath Ramalingaiah Munnan, Raghu Ravindran, Ravi Shekhar
  • Patent number: 8804571
    Abstract: In some embodiments, an apparatus includes a first network control entity configured to be implemented at a first edge device. The first network control entity is configured to receive a control packet from a peripheral processing device via a tunnel that is between the peripheral processing device and the first network control entity and that includes at least a portion within a second edge device. The first network control entity is configured to determine routing information associated with the peripheral processing device based on the control packet. The first network control entity is configured to send the routing information to a second network control entity such that the second network control entity routes a data unit addressed to the peripheral processing device to the second edge device without sending the data unit to the first edge device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 12, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Manoj Tiwari, Ravi Shekhar, Quaizar Vohra, Ronak Shah, Prasennaram Dhanushkodi
  • Patent number: 8718063
    Abstract: In some embodiments, an apparatus includes a first network device configured to receive, from a second network device, a first forwarding-state packet associated with a peripheral processing device and having a first generation identifier. The first network device is configured to receive, from a third network device, a second forwarding-state packet associated with the peripheral processing device and having a second generation identifier. The first network device is configured to implement forwarding-state information included in the first forwarding-state packet based on a comparison of the first generation identifier and the second generation identifier.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 6, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Ravi Shekhar, Jaihari Loganathan, Jeelani Syed, Rahul Aggarwal
  • Patent number: 8717909
    Abstract: In some embodiments, an apparatus includes a route reflector implemented in at least one of a memory or a processing device. The route reflector is configured to be included within a switch fabric system. The route reflector is configured to receive, from a network management module, an instruction to install a route associated with a multi-stage switch, and send the instruction to install to a route target network control entity associated with the multi-stage switch. The route reflector is also configured to receive, from the route target network control entity, a first acknowledgement signal indicating that the route was successfully installed at the route target network control entity. The route reflector is configured to send a second acknowledgement signal to the network management module in response to receiving the first acknowledgement signal.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: May 6, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Ravi Shekhar, Jaihari Loganathan
  • Patent number: 8694654
    Abstract: In one embodiment, an apparatus includes a first network control entity associated with at least a portion of multiple physical ports at a first access switch that are operatively coupled to a peripheral processing device and a switch fabric. The first network control entity can receive a host protocol request from the peripheral processing device, the first network control entity to transmit the host protocol request to a second network control entity associated with at least a portion of multiple physical ports at a second access switch, such that the host protocol request causes the second network control entity to obtain a response to the host protocol request. The first network control entity can receive the response to the host protocol request from the second network control entity and transmit the response to the host protocol request to the peripheral processing device.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 8, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Vijayabhaskar Annamalai Kalusivalingam, Jaihari Loganathan, Sreekanth Reddy, Ravi Shekhar, Jeelani Syed, Quaizar Vohra
  • Patent number: 8615015
    Abstract: An apparatus includes a memory configured to store multiple route descriptors as a tree, a communications interface configured to be in communication with an access switch, and a processor operatively coupled to the memory and the communications interface. Each route descriptor is a node within the tree, and includes a next hop destination associated with a next hop destination of a route associated with that route descriptor and a next hop indicator associated with a quantity of routes represented by that route descriptor. A first route descriptor has a first child route descriptor and a second child route descriptor. The processor is configured to define, at a first time, a value of the next hop destination of the first route descriptor and to send, at a second time after the first time, the value of the next hop destination of the first route descriptor to the access switch.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 24, 2013
    Assignee: Juniper Networks, Inc.
    Inventor: Ravi Shekhar
  • Patent number: 8560660
    Abstract: In some embodiments, an apparatus implemented in a memory and/or a processing device includes a first network control entity to manage a first data plane module associated with a port from a set of ports at a first access switch. The first network control entity associates an identifier of a peripheral processing device operatively coupled to the port from the set of ports with a next hop reference. The first network control entity provides the next hop reference to a second network control entity that manages a second data plane module at a second access switch such that the second data plane module can append the next hop reference to a data packet when the peripheral processing device is within a data path between and including the second access switch and a destination peripheral processing device.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 15, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Vijayabhaskar Annamalai Kalusivalingam, Quaizar Vohra, Ravi Shekhar, Jaihari Loganathan
  • Publication number: 20130163607
    Abstract: In some embodiments, a system includes a set of network control entities associated with a distributed multi-stage switch. Each network control entity from the set of network control entities is configured to manage at least one edge device having a set of ports and coupled to the distributed multi-stage switch. Each network control entity from the set of network control entities is associated with a unique set of identifiers. A network control entity from the set of network control entities is configured to assign a unique identifier from its unique set of identifiers to a port from the set of ports of the at least one edge device in response to the network control entity receiving a login request associated with the port.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: Juniper Networks, Inc.
    Inventors: Amit Shukla, Suresh Boddapati, Joseph White, Ravi Shekhar, Jeevan Kamisetty
  • Publication number: 20130163591
    Abstract: In some embodiments, an apparatus includes a management module configured to assign a unique set of identifiers to each network control entity from a set of network control entities. As a result, a network control entity from the set of network control entities can assign an identifier from its unique set of identifiers to a port in response to that network control entity receiving a login request from the port. The set of network control entities is associated with a distributed multi-stage switch. The management module is also configured to store a zone set database associated with the distributed multi-stage switch. The management module is configured to send an instance of an active zone set stored within the zone set database to each network control entity from the set of network control entities such that each network control entity can enforce the active zone set.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: Juniper Networks, Inc.
    Inventors: Amit Shukla, Joseph White, Ravi Shekhar, Jeevan Kamisetty
  • Publication number: 20120189009
    Abstract: In some embodiments, an apparatus includes a first network device configured to receive, from a second network device, a first forwarding-state packet associated with a peripheral processing device and having a first generation identifier. The first network device is configured to receive, from a third network device, a second forwarding-state packet associated with the peripheral processing device and having a second generation identifier. The first network device is configured to implement forwarding-state information included in the first forwarding-state packet based on a comparison of the first generation identifier and the second generation identifier.
    Type: Application
    Filed: July 25, 2011
    Publication date: July 26, 2012
    Applicant: Juniper Networks, Inc.
    Inventors: Ravi Shekhar, Jaihari Loganathan, Jeelani Syed, Rahul Aggarwal
  • Publication number: 20120158942
    Abstract: In some embodiments, a system includes a first network control entity, a second network control entity and a third network control entity. The first network control entity and the second network control entity are associated with a first network segment. The third network control entity is associated with a second network segment. The first network control entity is operable to send to the second network control entity an identifier of the first network segment and forwarding-state information associated with a data port at a first network element. The second network control entity is operable to receive the identifier of the first network segment and the forwarding-state information. The second network control entity is operable to send the forwarding-state information to a second network element. The first network control entity does not send the identifier of the first network segment and the forwarding-state information to the third network control entity.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Applicant: Juniper Networks, Inc.
    Inventors: Vijayabhaskar Annamalai Kalusivalingam, Jaihari Loganathan, Ravi Shekhar, Jeelani Syed, Quaizar Vohra
  • Publication number: 20120158930
    Abstract: In some embodiments, an apparatus implemented in a memory and/or a processing device includes a first network control entity to manage a first data plane module associated with a port from a set of ports at a first access switch. The first network control entity associates an identifier of a peripheral processing device operatively coupled to the port from the set of ports with a next hop reference. The first network control entity provides the next hop reference to a second network control entity that manages a second data plane module at a second access switch such that the second data plane module can append the next hop reference to a data packet when the peripheral processing device is within a data path between and including the second access switch and a destination peripheral processing device.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Applicant: Juniper Networks, Inc.
    Inventors: Vijayabhaskar Annamalai Kalusivalingam, Quaizar Vohra, Ravi Shekhar, Jaihari Loganathan
  • Publication number: 20120069842
    Abstract: In some embodiments, a non-transitory processor-readable medium stores code representing instructions configured to cause a processor to receive, from an access switch, a first signal including forwarding state information associated with a first peripheral processing device from a set of peripheral processing devices. The code can further represent instructions configured to cause the processor to receive, from the first peripheral processing device, a second signal including a data packet. The code can further represent instructions configured to cause the processor to send, to a replication engine associated with the set of peripheral processing devices, a third signal such that the replication engine (1) defines a copy of the data packet, which is included within the third signal, and (2) sends, to a second peripheral processing device from the set of peripheral processing devices, a fourth signal including the copy of the data packet.
    Type: Application
    Filed: March 22, 2011
    Publication date: March 22, 2012
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Sreekanth REDDY, Ravi SHEKHAR, Jeelani SYED, Quaizar VOHRA
  • Publication number: 20110238816
    Abstract: In some embodiments, a network management module is operatively coupled to a set of edge devices that are coupled to a set of peripheral processing devices. The network management module can receive a signal associated with a broadcast protocol from an edge device from the set of edge devices in response to that edge device being operatively coupled to a switch fabric. The network management module can provision that edge device in response to receiving the signal. The network management module can define multiple network control entities at the set of edge devices such that each network control entity from the multiple network control entities can provide forwarding-state information associated with at least one peripheral processing device from the set of peripheral processing devices to at least one remaining network control entity from the multiple network control entities using a selective protocol.
    Type: Application
    Filed: December 15, 2010
    Publication date: September 29, 2011
    Applicant: Juniper Networks, Inc.
    Inventors: Quaizar Vohra, Ravi Shekhar, Umesh Kondur, Arijit Sarcar