Patents by Inventor Ravi Sridhara
Ravi Sridhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230258699Abstract: In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.Type: ApplicationFiled: April 25, 2023Publication date: August 17, 2023Inventors: Abdellatif BELLAOUAR, Arul BALASUBRAMANIYAN, Gurkanwal Singh SAHOTA, Muhammad HASSAN, Jorge GARCIA, Bhushan Shanti ASURI, Ravi SRIDHARA, Omar Essam EL-AASSAR, Chinmaya MISHRA
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Publication number: 20230253346Abstract: In certain aspects, a chip includes a pad, and a power amplifier having a first output and a second output. The chip also includes a transformer, wherein the transformer includes a first inductor coupled between a first terminal and a second terminal of the transformer, wherein the first terminal is coupled to the first output of the power amplifier, and the second terminal is coupled to the second output of the power amplifier. The transformer also includes a second inductor coupled between a third terminal and a fourth terminal of the transformer, wherein the third terminal is coupled to the pad. The chip also includes a first switch coupled to the fourth terminal, a shunt inductor coupled in parallel with the first switch, and a low-noise amplifier coupled to the third terminal.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Inventors: Muhammad HASSAN, Bhushan Shanti ASURI, Jeremy Darren DUNWORTH, Ravi SRIDHARA
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Patent number: 11656254Abstract: In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.Type: GrantFiled: July 17, 2020Date of Patent: May 23, 2023Assignee: QUALCOMM IncorporatedInventors: Abdellatif Bellaouar, Arul Balasubramaniyan, Gurkanwal Singh Sahota, Muhammad Hassan, Jorge Garcia, Bhushan Shanti Asuri, Ravi Sridhara, Omar Essam El-Aassar, Chinmaya Mishra
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Patent number: 11646277Abstract: According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.Type: GrantFiled: December 10, 2020Date of Patent: May 9, 2023Assignee: QUALCOMM IncorporatedInventors: Muhammad Hassan, Bhushan Shanti Asuri, Jeremy Darren Dunworth, Ravi Sridhara
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Patent number: 11380988Abstract: In some aspects, an apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier coupled to the first inductor, a first antenna coupled to a first terminal of the second inductor, a second antenna coupled to a second terminal of the second inductor, a first switch coupled between the first terminal of the second inductor and a ground, a second switch coupled between the second terminal of the second inductor and the ground, and a low-noise amplifier coupled to the third inductor.Type: GrantFiled: November 13, 2020Date of Patent: July 5, 2022Assignee: QUALCOMM IncorporatedInventors: Muhammad Hassan, Jeremy Goldblatt, Bhushan Shanti Asuri, Jeremy Darren Dunworth, Abdellatif Bellaouar, Ravi Sridhara, Jorge Garcia
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Publication number: 20220189886Abstract: According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Inventors: Muhammad HASSAN, Bhushan Shanti ASURI, Jeremy Darren DUNWORTH, Ravi SRIDHARA
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Publication number: 20220158343Abstract: In some aspects, an apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier coupled to the first inductor, a first antenna coupled to a first terminal of the second inductor, a second antenna coupled to a second terminal of the second inductor, a first switch coupled between the first terminal of the second inductor and a ground, a second switch coupled between the second terminal of the second inductor and the ground, and a low-noise amplifier coupled to the third inductor.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Muhammad HASSAN, Jeremy GOLDBLATT, Bhushan Shanti ASURI, Jeremy Darren DUNWORTH, Abdellatif BELLAOUAR, Ravi SRIDHARA, Jorge GARCIA
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Publication number: 20220018882Abstract: In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.Type: ApplicationFiled: July 17, 2020Publication date: January 20, 2022Inventors: Abdellatif BELLAOUAR, Arul BALASUBRAMANIYAN, Gurkanwal Singh SAHOTA, Muhammad HASSAN, Jorge GARCIA, Bhushan Shanti ASURI, Ravi SRIDHARA, Omar Essam EL-AASSAR, Chinmaya MISHRA
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Patent number: 10659010Abstract: An RF driver circuit may include a wideband output impedance matching and gain circuit, a wideband input impedance matching and gain circuit, and a summer configured to sum the outputs of the wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit. The wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit may collectively provide the gain of the RF driver circuit. The wideband output impedance matching circuit may have a source follower configuration. The wideband input impedance matching circuit may have a common gate configuration. Controllable bias voltages may be used to maintain a constant gain and interface impedances in multiple modes of operation.Type: GrantFiled: January 23, 2019Date of Patent: May 19, 2020Assignee: QUALCOMM IncorporatedInventors: Chirag Dipak Patel, Lai Kan Leung, Ravi Sridhara
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Patent number: 10469122Abstract: Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.Type: GrantFiled: January 16, 2018Date of Patent: November 5, 2019Assignee: QUALCOMM IncorporatedInventors: Chirag Dipak Patel, Lai Kan Leung, Zhang Jin, Chinmaya Mishra, Ravi Sridhara, Youngchang Yoon
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Patent number: 10193580Abstract: Devices and techniques are described to extract specific frequency band signals from a wide-band radio-frequency signal. A network entity may include an antenna for receiving the wide-band radio-frequency signal and may include a receiver circuit for processing the wide-band radio-frequency signal. The receiver circuit may include a transconductance amplifier and a plurality of single-band circuits. The transconductance amplifier may be configured to generate an amplified wide-band radio-frequency signal and send it to one or more of the single-band circuits. Each single-band circuit may be configured to extract a different frequency band signal from the amplified wide-band radio-frequency signal.Type: GrantFiled: March 20, 2018Date of Patent: January 29, 2019Assignee: QUALCOMM IncorporatedInventors: Chirag Dipak Patel, Lai Kan Leung, Xinmin Yu, Timothy Donald Gathman, Ravi Sridhara
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Publication number: 20180278277Abstract: Devices and techniques are described to extract specific frequency band signals from a wide-band radio-frequency signal. A network entity may include an antenna for receiving the wide-band radio-frequency signal and may include a receiver circuit for processing the wide-band radio-frequency signal. The receiver circuit may include a transconductance amplifier and a plurality of single-band circuits. The transconductance amplifier may be configured to generate an amplified wide-band radio-frequency signal and send it to one or more of the single-band circuits. Each single-band circuit may be configured to extract a different frequency band signal from the amplified wide-band radio-frequency signal.Type: ApplicationFiled: March 20, 2018Publication date: September 27, 2018Inventors: Chirag Dipak Patel, Lai Kan Leung, Xinmin Yu, Timothy Donald Gathman, Ravi Sridhara
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Publication number: 20180205413Abstract: Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.Type: ApplicationFiled: January 16, 2018Publication date: July 19, 2018Inventors: Chirag Dipak PATEL, Lai Kan LEUNG, Zhang JIN, Chinmaya MISHRA, Ravi SRIDHARA, Youngchang YOON
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Patent number: 9973182Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.Type: GrantFiled: September 14, 2016Date of Patent: May 15, 2018Assignee: QUALCOMM IncorporatedInventors: Animesh Paul, Jingcheng Zhuang, Xinhua Chen, Ravi Sridhara
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Publication number: 20180076805Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.Type: ApplicationFiled: September 14, 2016Publication date: March 15, 2018Inventors: Animesh PAUL, Jingcheng ZHUANG, Xinhua CHEN, Ravi SRIDHARA
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Patent number: 9893875Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.Type: GrantFiled: September 20, 2016Date of Patent: February 13, 2018Assignee: QUALCOMM IncorporatedInventors: Marco Zanuso, Mohammad Elbadry, Tsai-Pi Hung, Ravi Sridhara, Francesco Gatta, Jingcheng Zhuang
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Publication number: 20170338940Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.Type: ApplicationFiled: September 20, 2016Publication date: November 23, 2017Inventors: Marco ZANUSO, Mohammad ELBADRY, Tsai-Pi HUNG, Ravi SRIDHARA, Francesco GATTA, Jingcheng ZHUANG
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Patent number: 8929840Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.Type: GrantFiled: September 11, 2008Date of Patent: January 6, 2015Assignee: QUALCOMM IncorporatedInventors: Sankaran Aniruddhan, Chiewcharn Narathong, Sriramgopal Sridhara, Ravi Sridhara, Gurkanwal Singh Sahota, Frederic Bossu, Ojas M. Choksi
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Patent number: 8599938Abstract: Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.Type: GrantFiled: November 25, 2008Date of Patent: December 3, 2013Assignee: QUALCOMM IncorporatedInventors: Sankaran Aniruddhan, Chiewcharn Narathong, Ravi Sridhara, Babak Nejati
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Patent number: 8270499Abstract: A receiver with a balanced I/Q transformer is described. In an exemplary design, the receiver includes an LNA that amplifies a received RF signal and provides a single-ended RF signal to the balanced I/Q transformer. The balanced I/Q transformer includes at least one primary coil and first and second secondary coils. The first secondary coil is magnetically coupled to the at least one primary coil and provides a first differential RF signal to a first mixer. The second secondary coil is magnetically coupled to the at least one primary coil and provides a second differential RF signal to a second mixer. The first and second mixers downconvert the first and second differential RF signals with I and Q LO signals, respectively, and provide differential I and Q downconverted signals. The primary and secondary coils may be fabricated on two conductive layers of an integrated circuit.Type: GrantFiled: May 15, 2009Date of Patent: September 18, 2012Assignee: QUALCOMM, IncorporatedInventors: Li-Chung Chang, Maulin P. Bhagat, Hanil Lee, Ravi Sridhara