Patents by Inventor Ravi Srinivasa Vedula

Ravi Srinivasa Vedula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for I/O synthesis and for assigning I/O to programmable devices
    Patent number: 7992121
    Abstract: A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin definition to a first pin of the PD based on the electrical constraint, the logical constraint, and the group constraint; identifying a first pin of the EC to connect with the first pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and a connection preference; generating a first connection between the first pin of the EC and a second pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and the connection preference; and storing the first connection in an edge list.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: August 2, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nagesh Chandrasekaran Gupta, Ravi Srinivasa Vedula
  • SYSTEM AND METHOD FOR I/O SYNTHESIS AND FOR ASSIGNING I/O TO PROGRAMMABLE DEVICES
    Publication number: 20090178017
    Abstract: A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin definition to a first pin of the PD based on the electrical constraint, the logical constraint, and the group constraint; identifying a first pin of the EC to connect with the first pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and a connection preference; generating a first connection between the first pin of the EC and a second pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and the connection preference; and storing the first connection in an edge list.
    Type: Application
    Filed: January 9, 2009
    Publication date: July 9, 2009
    Applicant: TARAY TECHNOLOGIES (INDIA) PRIVATE LIMITED
    Inventors: Nagesh Chandrasekaran Gupta, Ravi Srinivasa Vedula