Abstract: The print engine is composed of a semiconductor memory layer overlaid on an insulated conductive layer with a one to one correspondence of each memory cell with the conductive pad on the insulated layer. The entire structure can be fashioned into a either a planar structure or a cylindrical structure with insulated conductive pads providing protection to the sensitive semiconductor memory from impact loading that occurs during the printing process.

Abstract: A print engine suitable for printing barcodes and other patterns using charged inks includes a semiconductor memory layer having memory circuits that are coupled to one or more line elements and/or printel cells. The printel cells and line elements either attract or do not attract charged ink based on the data stored in the corresponding memory circuit. The line elements and printel cells may be configured to form a linear barcode or a 2-dimensional barcode. The charged ink may also be electrically conducting and the line elements and printel cells may be configured to form electrical structures such as electrical circuits or antennae. The charged ink may also be electrically semiconducting and by the line elements and printel cells may be configured to form electronic semiconductor devices and circuits.

Abstract: An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

Abstract: A smart surface is composed of a semiconductor memory layer overlaid on an insulated conductive layer with a one to one correspondence of each memory cell with the conductive pad on the insulated layer. The entire structure can be fashioned into a either a planar structure or other geometric structure. An appliance may be overlaid the smart surface and signals transmitted and received to and from the appliance via the conductive pad(s) of the smart surface.

Abstract: The print engine is composed of a semiconductor memory layer overlaid on an insulated conductive layer with a one to one correspondence of each memory cell with the conductive pad on the insulated layer. The entire structure can be fashioned into a either a planar structure or a cylindrical structure with insulated conductive pads providing protection to the sensitive semiconductor memory from impact loading that occurs during the printing process.

Abstract: A print engine suitable for printing barcodes and other patterns using charged inks includes a semiconductor memory layer having memory circuits that are coupled to one or more line elements and/or printel cells. The printel cells and line elements either attract or do not attract charged ink based on the data stored in the corresponding memory circuit. The line elements and printel cells may be configured to form a linear barcode or a 2-dimensional barcode. The charged ink may also be electrically conducting and the line elements and printel cells may be configured to form electrical structures such as electrical circuits or antennae. The charged ink may also be electrically semiconducting and by the line elements and printel cells may be configured to form electronic semiconductor devices and circuits.

Abstract: An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signals embedded in the synchronized signal to determine a bit leak rate of bits from an elastic store following a pointer adjustment event such that the elastic store provides as an output a more-uniformly-distributed-gapped data stream.

Abstract: A structure and process are provided for using a single wire or data bus to detect collisions between two communication nodes connected by the single wire by sensing current changes in the wire, where large current changes indicate a collision. When a second node wants to obtain control of the wire on which a first node is transmitting data, the second node transmits a special data packet to ensure a collision and cause a large current to flow on the wire. Once a large current is detected in the wire to indicate a bit difference or collision, the first node stops transmitting and waits until it receives a synchronization bit pattern, which will indicate that the special data packet transmitted by the second node has ended. The two nodes are now synchronized, such that the second node has control of the wire and can begin transmission of a data packet. In order to indicate a collision, the large current flow must remain high after a specified time interval, such as a clock cycle.

Abstract: The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator.

Abstract: An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

Abstract: An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signals embedded in the synchronized signal to determine a bit leak rate of bits from an elastic store following a pointer adjustment event such that the elastic store provides as an output a more-uniformly-distributed-gapped data stream.

Abstract: The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

Abstract: The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

Abstract: A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A second region (22) of the masking layer (14) is etched to form a single opening or a second plurality of openings different in geometry from the first plurality of openings. A single ion implant step or an equivalent doping step is used to dope exposed portions of the substrate (12). The geometric differences in the masking layer (14) between region (20) and region (22) results in the formation of the first and second doped regions (24 and 26) wherein the first and second doped regions (24 and 26) vary in doping uniformity, doping concentration, and doping junction depth.