Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode.

Abstract: A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

Abstract: A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired.

Abstract: An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

Abstract: A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

Abstract: The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.

Abstract: A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

Abstract: A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.

Abstract: A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer portions of the first insulating layer define the gate opening. A gate dielectric layer is formed over the substrate in the gate opening. A conductive layer is formed over the substrate. The conductive layer fills the gate opening and the source/drain (S/D) openings. The conductive layer is doped with dopants. The conductive layer is planarized to form a gate over the gate dielectric layer and filling the gate opening and filling the source/drain (S/D) opening to form elevated source/drain (S/D) regions. The conductive layer is preferably planarized so that the top surface of the conductive layer is level with the top surface of the first insulating layer. The spacer portions are removed to form spacer openings.

Abstract: A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a portion of the exposed substrate portion within the patterned layer opening on the patterned layer exposed sidewalls. The internal spacers being comprised of a WF1 material having a first work function. A planarized gate electrode body is formed within the remaining portion of the patterned layer opening and adjacent to the internal spacers. The gate electrode body being comprised of a WF2 material having a second work function. The internal spacers and the gate electrode body forming the gate electrode.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction.

Abstract: A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction.