Patents by Inventor Ravi Sunkavalli
Ravi Sunkavalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11726936Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.Type: GrantFiled: December 3, 2021Date of Patent: August 15, 2023Inventors: Chandrasekhar S. Thyamagondlu, Darren Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma
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Publication number: 20220092010Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.Type: ApplicationFiled: December 3, 2021Publication date: March 24, 2022Applicant: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Darren Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma
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Patent number: 11232053Abstract: A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.Type: GrantFiled: June 9, 2020Date of Patent: January 25, 2022Assignee: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Darren Jue, Ravi Sunkavalli, Akhil Krishnan, Tao Yu, Kushagra Sharma
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Patent number: 11194490Abstract: A circuit arrangement includes a memory circuit, data upload circuitry, data formatting circuitry, and a systolic array (SA). The data upload circuitry inputs a multi-dimensional data set and stores the multi-dimensional data set in the memory circuit. The data formatting circuitry reads subsets of the multi-dimensional data set from the memory circuit. The data formatting circuitry arranges data elements of the subsets into data streams, and outputs data elements in the data streams in parallel. The SA includes rows and columns of multiply-and-accumulate (MAC) circuits. The SA inputs data elements of the data streams to columns of MAC circuits in parallel, inputs filter values to rows of MAC circuits in parallel, and computes an output feature map from the data streams and the filter values.Type: GrantFiled: April 18, 2018Date of Patent: December 7, 2021Assignee: XILINX, INC.Inventors: Ravi Sunkavalli, Victor J. Wu, Poching Sun
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Patent number: 10990547Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.Type: GrantFiled: August 11, 2019Date of Patent: April 27, 2021Assignee: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
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Patent number: 10983920Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.Type: GrantFiled: February 8, 2018Date of Patent: April 20, 2021Assignee: XILINX, INC.Inventors: Chandrasekhar S Thyamagondlu, Darren Jue, Tao Yu, John West, Hanh Hoang, Ravi Sunkavalli
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Publication number: 20210042252Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.Type: ApplicationFiled: August 11, 2019Publication date: February 11, 2021Applicant: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
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Patent number: 10725942Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.Type: GrantFiled: November 9, 2018Date of Patent: July 28, 2020Assignee: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Ravi N. Kurlagunda, Kenneth K. Chan, Ravi Sunkavalli
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Patent number: 10659437Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.Type: GrantFiled: September 27, 2018Date of Patent: May 19, 2020Assignee: Xilinx, Inc.Inventors: Ravi Sunkavalli, Anujan Varma, Chuan Cheng Pan, Patrick C. McCarthy, Hanh Hoang
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Publication number: 20200151120Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: Xilinx, Inc.Inventors: Chandrasekhar S. Thyamagondlu, Ravi N. Kurlaganda, Kenneth K. Chan, Ravi Sunkavalli
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Publication number: 20200143088Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.Type: ApplicationFiled: September 27, 2018Publication date: May 7, 2020Applicant: Xilinx, Inc.Inventors: Ravi Sunkavalli, Anujan Varma, Chuan Cheng Pan, Patrick C. McCarthy, Hanh Hoang
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Publication number: 20190243781Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.Type: ApplicationFiled: February 8, 2018Publication date: August 8, 2019Applicant: Xilinx, Inc.Inventors: Chandrasekhar S Thyamagondlu, Darren Jue, Tao Yu, John West, Hanh Hoang, Ravi Sunkavalli
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Patent number: 9455036Abstract: A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.Type: GrantFiled: September 28, 2015Date of Patent: September 27, 2016Assignee: Adesto Technologies CorporationInventors: Ed McKernan, Malcolm Wing, Ravi Sunkavalli
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Patent number: 9443584Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.Type: GrantFiled: December 17, 2012Date of Patent: September 13, 2016Assignee: Adesto Technologies CorporationInventors: Ravi Sunkavalli, Malcolm Wing
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Patent number: 9208870Abstract: A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports.Type: GrantFiled: September 13, 2012Date of Patent: December 8, 2015Assignee: Adesto Technologies CorporationInventor: Ravi Sunkavalli
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Patent number: 9147464Abstract: A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path.Type: GrantFiled: March 18, 2013Date of Patent: September 29, 2015Assignee: Adesto Technologies CorporationInventors: Ed McKernan, Malcolm Wing, Ravi Sunkavalli
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Patent number: 9047975Abstract: Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.Type: GrantFiled: November 28, 2012Date of Patent: June 2, 2015Assignee: Adesto Technologies CorporationInventors: Ravi Sunkavalli, Malcolm Wing
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Patent number: 8982602Abstract: A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.Type: GrantFiled: August 30, 2012Date of Patent: March 17, 2015Assignee: Adesto Technologies CorporationInventors: Ravi Sunkavalli, Malcolm Wing
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Patent number: 8933734Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: January 21, 2014Date of Patent: January 13, 2015Assignee: Achronix Semiconductor CorporationInventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Patent number: 8902631Abstract: A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.Type: GrantFiled: August 30, 2012Date of Patent: December 2, 2014Assignee: Adesto Technologies CorporationInventors: Ravi Sunkavalli, Ishai Naveh, Malcolm Wing