Abstract: Techniques for validating configuration changes in a mixed node topology are provided. In one embodiment, a device can identify a link to be removed from a topology comprising a plurality of nodes, where the plurality of nodes includes one or more nodes of a first type and one or more nodes of a second type. The device can then determine whether the removal of the link from the topology would require data traffic between two nodes of the first type to pass through a node of the second type.

Abstract: A framework for reliably communicating port information in a system of devices is provided. In one embodiment, each device in the system of devices can create a first record that includes port information pertaining to a plurality of ports of the device, where the plurality of ports are usable for communicatively coupling the device to other devices in the system of devices. The device can further receive, from the other devices in the system of devices, one or more second records including port information pertaining to the ports of the other devices, and can store the first record and the one or more second records in a data store maintained locally on the device. The device can then forward copies of the first record and the one or more second records out of each of the plurality of ports, thereby causing the copies of the first record and the one or more second records to be communicated to the other devices in the system of devices.

Abstract: In one embodiment, a network device is provided that includes a plurality of ports, where each port is associated with a plurality of traffic classes for prioritizing traffic received on the port. The network device further includes a packet buffer memory, an ingress traffic management engine, and an egress traffic management engine. The network device is configured to allow, for each port, concurrent operation of tail-drop and priority-based flow control (PFC) with respect to different traffic classes of the port.

Abstract: Techniques for assigning device identifiers in a system of devices are provided. In one embodiment, a master device of the system can maintain a first configuration that specifies a set of links between a first subset of the devices, where the first configuration includes a device identifier for each device in the first subset. The master device can further generate a second configuration that specifies a set of links between a second subset of the devices, where the second configuration is based on a physical topology of the system, and where one or more devices in the second subset are unknown devices that are not associated with a device identifier in the physical topology. The master device can then assign device identifiers to the unknown devices in the second subset by comparing the first configuration with the second configuration.

Abstract: Techniques for automatically configuring a network device are provided. In one embodiment, the network device can receive a Layer 2 discovery packet on an uplink port operable for connecting the network device to another network device. The network device can then learn VLAN information from the Layer 2 discovery packet and automatically configure one or more of its ports based on the VLAN information.

Abstract: Techniques for validating configuration changes in a mixed node topology are provided. In one embodiment, a device can identify a link to be removed from a topology comprising a plurality of nodes, where the plurality of nodes includes one or more nodes of a first type and one or more nodes of a second type. The device can then determine whether the removal of the link from the topology would require data traffic between two nodes of the first type to pass through a node of the second type.

Abstract: Techniques for validating configuration changes in a mixed node topology are provided. In one embodiment, a device can identify a link to be removed from a topology comprising a plurality of nodes, where the plurality of nodes includes one or more nodes of a first type and one or more nodes of a second type. The device can then determine whether the removal of the link from the topology would require data traffic between two nodes of the first type to pass through a node of the second type.

Abstract: A framework for reliably communicating port information in a system of devices is provided. In one embodiment, each device in the system of devices can create a first record that includes port information pertaining to a plurality of ports of the device, where the plurality of ports are usable for communicatively coupling the device to other devices in the system of devices. The device can further receive, from the other devices in the system of devices, one or more second records including port information pertaining to the ports of the other devices, and can store the first record and the one or more second records in a data store maintained locally on the device. The device can then forward copies of the first record and the one or more second records out of each of the plurality of ports, thereby causing the copies of the first record and the one or more second records to be communicated to the other devices in the system of devices.

Abstract: Techniques for automatically configuring a network device are provided. In one embodiment, the network device can receive a Layer 2 discovery packet on an uplink port operable for connecting the network device to another network device. The network device can then learn VLAN information from the Layer 2 discovery packet and automatically configure one or more of its ports based on the VLAN information.

Abstract: In one embodiment, a network device is provided that includes a plurality of ports, where each port is associated with a plurality of traffic classes for prioritizing traffic received on the port. The network device further includes a packet buffer memory, an ingress traffic management engine, and an egress traffic management engine. The network device is configured to allow, for each port, concurrent operation of tail-drop and priority-based flow control (PFC) with respect to different traffic classes of the port.

Abstract: Techniques for validating configuration changes in a mixed node topology are provided. In one embodiment, a device can identify a link to be removed from a topology comprising a plurality of nodes, where the plurality of nodes includes one or more nodes of a first type and one or more nodes of a second type. The device can then determine whether the removal of the link from the topology would require data traffic between two nodes of the first type to pass through a node of the second type.

Abstract: Techniques for assigning device identifiers in a system of devices are provided. In one embodiment, a master device of the system can maintain a first configuration that specifies a set of links between a first subset of the devices, where the first configuration includes a device identifier for each device in the first subset. The master device can further generate a second configuration that specifies a set of links between a second subset of the devices, where the second configuration is based on a physical topology of the system, and where one or more devices in the second subset are unknown devices that are not associated with a device identifier in the physical topology. The master device can then assign device identifiers to the unknown devices in the second subset by comparing the first configuration with the second configuration.

Abstract: In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted.

Abstract: A time multiplexing technique and corresponding circuitry is described which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

Abstract: A time multiplexing technique and corresponding circuitry which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

Abstract: A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.