Patents by Inventor Ravi Tanikella

Ravi Tanikella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit and process for fabricating thereof
    Patent number: 9941158
    Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 10, 2018
    Assignee: INTEL CORPORATION
    Inventors: Charan Gurumurthy, Islam Salama, Houssam Jomaa, Ravi Tanikella
  • INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF
    Publication number: 20110298135
    Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Inventors: Charan Gurumurthy, Islam Salama, Houssam Jomaa, Ravi Tanikella
  • Integrated circuit and process for fabricating thereof
    Patent number: 7998857
    Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventors: Charan Gurumurthy, Islam Salama, Houssam Jomaa, Ravi Tanikella
  • INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF
    Publication number: 20090108455
    Abstract: A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.
    Type: Application
    Filed: October 24, 2007
    Publication date: April 30, 2009
    Applicant: INTEL CORPORATION
    Inventors: Charan Gurumurthy, Islam Salama, Houssam Jomaa, Ravi Tanikella