Patents by Inventor Ravi V. Mahajan
Ravi V. Mahajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145395Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
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Publication number: 20230130944Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: December 27, 2022Publication date: April 27, 2023Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Publication number: 20230040850Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Patent number: 11515248Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: September 1, 2020Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20200395297Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: September 1, 2020Publication date: December 17, 2020Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Patent number: 10796988Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: June 7, 2018Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 9941246Abstract: An electronic assembly that includes a first electronic device. The first electronic device includes a cavity that extends into a back side of the first electronic device. The electronic assembly further includes a second electronic device. The second electronic device is mounted to the first electronic device within the cavity in the first electronic device. In some example forms of the electronic assembly, the first electronic device and the second electronic device are each a die. It should be noted that other forms of the electronic assembly are contemplated where only one of the first electronic device and the second electronic device is a die. In some forms of the electronic assembly, the second electronic device is soldered to the first electronic device.Type: GrantFiled: July 2, 2014Date of Patent: April 10, 2018Assignee: Intel CorporationInventors: Nitin Deshpande, Ravi V. Mahajan
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Patent number: 9820384Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.Type: GrantFiled: December 11, 2013Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Sasha Oster, Robert L. Sankman, Charles Gealer, Omkar Karhade, John S. Guzek, Ravi V. Mahajan, James C. Matayabas, Jr., Johanna Swan, Feras Eid, Shawna Liff, Timothy McIntosh, Telesphor Kamgaing, Adel Elsherbini, Kemal Aygun
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Publication number: 20160260688Abstract: An electronic assembly that includes a first electronic device. The first electronic device includes a cavity that extends into a back side of the first electronic device. The electronic assembly further includes a second electronic device. The second electronic device is mounted to the first electronic device within the cavity in the first electronic device. In some example forms of the electronic assembly, the first electronic device and the second electronic device are each a die. It should be noted that other forms of the electronic assembly are contemplated where only one of the first electronic device and the second electronic device is a die. In some forms of the electronic assembly, the second electronic device is soldered to the first electronic device.Type: ApplicationFiled: July 2, 2014Publication date: September 8, 2016Inventors: Nitin Deshpande, Ravi V. Mahajan
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Patent number: 9269701Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: August 5, 2015Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20150340353Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 9136236Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: September 28, 2012Date of Patent: September 15, 2015Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20150187681Abstract: This disclosure relates generally to a system and method including a substrate and an electronic component. The substrate includes a circuit board including a hole, a routing layer, and a first interconnect portion positioned, at least in part, within the hole. The electronic component includes a second interconnect portion, coupled to the first interconnect portion, forming an interconnect between the electronic component and the routing layer.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Inventors: Ravi V. Mahajan, Nitin Deshpande, John S. Guzek, Adel Elsherbini
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Publication number: 20150163921Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Inventors: Sasha Oster, Robert L. Sankman, Charles Gealer, Omkar Karhade, John S. Guzek, Ravi V. Mahajan, James C. Matayabas, JR., Johanna Swan, Feras Eid, Shawna Liff, Timothy McIntosh, Telesphor Teles Kamgaing, Adel Elsherbini, Kemal Aygun
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Publication number: 20140091474Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 7882624Abstract: To accommodate high power densities associated with high-performance integrated circuits, an integrated circuit (IC) package includes a heat-dissipating structure in which heat is dissipated from a surface of one or more dice to a heat spreader. The heat spreader has a fluid-conducting channel formed therein, and a fluid coolant may be circulated through the channel via a micropump. In an embodiment, the channel is located at or near a surface of the heat spreader, and a heat-generating IC is in thermal contact with the heat spreader. In an embodiment, the IC is a thinned die that is coupled to the heat spreader via a thinned thermal interface material. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.Type: GrantFiled: February 27, 2006Date of Patent: February 8, 2011Assignee: Intel CorporationInventors: Chuan Hu, Ravi V. Mahajan
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Patent number: 7851905Abstract: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.Type: GrantFiled: September 26, 2007Date of Patent: December 14, 2010Assignee: Intel CorporationInventors: Gregory M. Chrysler, Ravi V. Mahajan, Chia-Pin Chiu
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Publication number: 20090079063Abstract: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Gregory M. Chrysler, Ravi V. Mahajan, Chia-Pin Chiu
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Patent number: 7508671Abstract: A computer system and its method of cooling are provided. A vapor chamber serves as a heat spreader for heat from the microelectronic die. A thermoelectric module serves to cool the vapor chamber and maintain proper functioning of the vapor chamber, thus keeping the microelectronic die cooled. A controller receives input from five temperature sensors, and utilizes the input to control current to the thermoelectric module and voltage/current to a motor that drives a fan and provides additional cooling. A current sensor allows the controller to monitor and limit power provided to the thermoelectric module.Type: GrantFiled: October 10, 2003Date of Patent: March 24, 2009Assignee: Intel CorporationInventors: Ioan Sauciuc, Gregory M. Chrysler, Ravi V. Mahajan
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Patent number: RE44629Abstract: The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.Type: GrantFiled: November 30, 2004Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Suresh Ramalingam, Nagesh Vodrahalli, Michael J. Costello, Mun Leong Loke, Ravi V. Mahajan