Patents by Inventor Ravid Alon

Ravid Alon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240078088
    Abstract: A method, system, and product for performance analysis of quantum programs. A quantum program comprises plurality of code artifacts and is compilable into a quantum circuit. A representation of the quantum circuit that implements the quantum program is obtained. The quantum circuit manipulates a plurality of qubits over a plurality of cycles using a plurality of quantum gates. The representation of the quantum circuit includes circuit components. A performance measurement of a code artifact of the quantum program is automatically computed based on one or more circuit components that are mapped to the code artifact by a component to code mapping. The component to code mapping maps circuit components of the representation to the quantum circuit to respective code artifacts of the quantum program.
    Type: Application
    Filed: September 4, 2022
    Publication date: March 7, 2024
    Inventors: Amir Naveh, Yehuda Naveh, Ofek Kirzner, Shmuel Ur, Ravid Alon, Eyal Cornfeld, Avi Elazari, Lior Gazit
  • Publication number: 20230111236
    Abstract: A method, apparatus, a product comprising: obtaining a propagator module of a quantum function of a quantum program, the propagator module is programmed using a classical programming language, the propagator module configured to obtain as input a first domain of values for a first circuit parameter and a second domain of values for a second circuit parameter, and to output first and second sub-domains of the first and second domains of values, respectively; obtaining constraints of the quantum function; obtaining an optimization scheme that is defined over the first and second circuit parameters; generating a constraint problem based on the propagator module, the constraints, and the optimization scheme; resolving the constraint problem based on a constraint solver, a resolution comprising at least first and second values for the first and second circuit parameter; and synthesizing the quantum function according to the resolution.
    Type: Application
    Filed: October 31, 2022
    Publication date: April 13, 2023
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Adam Goldfeld, Nir Minerbi, Peleg Emanuel, Nati Erez, Israel Reichental
  • Publication number: 20230112525
    Abstract: A method, system and product comprising: obtaining a gate-level representation of a quantum circuit, wherein the gate-level representation comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation comprises a gate-level implementation of a functional block of a functional-level representation of the quantum circuit, wherein the functional block defines an operation of the quantum circuit over at least two cycles; obtaining metadata from a functional-level processing component, wherein the metadata comprise an artifact associated with the gate-level implementation of the functional block; and compiling the gate-level representation of the quantum circuit, wherein said compiling is performed based on the metadata.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Tal Goren, Nir Minerbi
  • Publication number: 20230111039
    Abstract: A method, system and product comprising: obtaining a functional-level representation of a quantum circuit that comprises a functional block; obtaining an indication of one or more resources that are available to the functional block, the indication regarding a range of cycles and an indication regarding a number of qubits; dynamically generating a gate-level implementation of the functional block that adheres to the indication of the one or more resources; and synthesizing a gate-level implementation of the quantum circuit, wherein the gate-level implementation of the quantum circuit comprises the gate-level implementation of the functional block.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Tal Goren, Adam Goldfeld, Jonatan Zimmermann, Nir Minerbi
  • Publication number: 20230111924
    Abstract: A method, system and product comprising: obtaining a functional-level representation of a quantum circuit that comprises a functional block, wherein the functional block defines an operation of the quantum circuit over at least two cycles; selecting from a function library an implementation for the functional block, wherein the function library comprises a plurality of alternative implementations of the functional block, wherein each implementation of the plurality of alternative implementations is configured to provide a same functionality of the functional block and is applicable to a quantum computer to be used for executing the quantum circuit; and generating a gate-level representation of the quantum circuit that comprises the implementation for the functional block.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Tal Goren, Adam Goldfeld, Nir Minerbi
  • Publication number: 20230115165
    Abstract: A method, system and product for synthesizing a quantum circuit using Constraint Satisfaction Problem (CSP). A functional-level representation of a quantum circuit that includes a first functional blocks and a second functional block is obtained. The functional-level representation defines a relationship between the first functional block and the second functional block. A CSP that is determined based on the functional-level representation, is automatically solved. The CSP is solved by identifying a first and second implementations to the first and second functional blocks that adhere to the CSP. A gate-level representation of the quantum circuit is synthesized using the first and second implementations.
    Type: Application
    Filed: May 24, 2022
    Publication date: April 13, 2023
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Tal Goren, Adam Goldfeld, Nir Minerbi
  • Publication number: 20230032530
    Abstract: A method, product and apparatus comprising: obtaining an indication of an execution task to be performed by a quantum computer, wherein the execution task comprises executing, by the quantum computer, a quantum program for a number of times that is larger than two times: obtaining a graph comprising nodes that are connected by edges, the graph represents a gate-level implementation of the quantum program, the graph depicts quantum restrictions of the quantum program; and packing multiple graphs according to the quantum restrictions to synthesize a joint circuit, the joint circuit is configured, when executed by the quantum computer, to implement the execution task, the multiple graphs comprise at least one instance of the graph, the one instance of the graph represents a single execution of the quantum program, whereby execution of the joint circuit implements execution of the quantum program for the number of times.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Inventors: Amir Naveh, Shmuel Ur, Eyal Cornfeld, Adam Goldfeld, Lior Gazit, Ravid Alon, Ofek Kirzner, Yehuda Naveh
  • Patent number: 11373114
    Abstract: A method, system and product comprising: obtaining a directed acyclic graph representing a quantum circuit, the directed acyclic graph comprising a set of blocks and connections therebetween, wherein a connection between a first block and a second block indicates passing an output value of a qubit outputted by the first block to be an input value of a qubit manipulated by the second block; determining a Constraint Satisfaction Problem (CSP) based on the directed acyclic graph, wherein the CSP comprises one or more constraints based on the connections defined by the directed acyclic graph; automatically solving the CSP, wherein said automatically solving comprises selecting an implementation to each block that adheres to the one or more constraints; and synthesizing a gate-level representation of the quantum circuit based on the solution to the CSP.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: June 28, 2022
    Assignee: CLASSIQ TECHNOLOGIES LTD.
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Tal Goren, Adam Goldfeld, Nir Minerbi
  • Patent number: 11281988
    Abstract: A method, system and product comprising: obtaining a functional-level representation of a quantum circuit that comprises a functional block; synthesizing a gate-level representation of the quantum circuit based on the functional-level representation of the quantum circuit, wherein the gate-level representation of the quantum circuit comprises a first sub-circuit and a second sub-circuit; providing the gate-level representation to a gate-level processing component; obtaining, from the gate-level processing component, a change indication indicating that the gate-level processing component modified the first sub-circuit, whereby determining a modified first sub-circuit; in response to the change indication, synthesizing a modified second sub-circuit based on a knowledge of an existence of the modified first sub-circuit.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: March 22, 2022
    Assignee: CLASSIQ TECHNOLOGIES LTD.
    Inventors: Amir Naveh, Shmuel Ur, Yehuda Naveh, Ofek Kirzner, Ravid Alon, Tal Goren, Nir Minerbi