Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.

Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off , during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.

Abstract: A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration.

Abstract: A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration.

Abstract: The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.

Abstract: The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a transition of a first clock signal and may assert the down signal indicating an occurrence of a transition of a second clock signal. The delay locked loop circuit further includes a delay circuit that may provide a plurality of delayed clock signals and an additional delayed clock signal, each corresponding to a delayed version of the first clock signal. Further, a false lock circuit may provide a reset signal to the detection circuit dependent upon whether a predetermined number of successive clock edges associated with the delayed clock signals occur within a given clock cycle of the first clock signal.