Patents by Inventor Ravikiran Kaidala Lakshman
Ravikiran Kaidala Lakshman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11625335Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.Type: GrantFiled: February 8, 2021Date of Patent: April 11, 2023Assignee: Cisco Technology, Inc.Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
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Publication number: 20210182212Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.Type: ApplicationFiled: February 8, 2021Publication date: June 17, 2021Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
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Patent number: 11036649Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.Type: GrantFiled: April 4, 2019Date of Patent: June 15, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: Ravikiran Kaidala Lakshman, Tanjore K. Suresh, Deepak Srinivas Mayya, Sagar Borikar
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Patent number: 10958597Abstract: The disclosed technology relates to a process for general-purpose ring buffer handling in a network controller. Specifically, general purpose ring buffers are used in software queue on both the host domain and the network controller to carry out user-defined protocols. The protocols define the relationship of the ring buffers in the host domain and the network controller domain (e.g. how data is moved and processed). The protocols minimize interruptions to the network controller. Furthermore, the implementation of ring buffers in the network controller domain also provides additional resources to the host domain for carrying out the user-defined protocols.Type: GrantFiled: February 25, 2019Date of Patent: March 23, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: Tanjore K Suresh, Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya
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Patent number: 10929310Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.Type: GrantFiled: March 1, 2019Date of Patent: February 23, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
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Patent number: 10908841Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.Type: GrantFiled: September 24, 2018Date of Patent: February 2, 2021Assignee: Cisco Technology, Inc.Inventors: Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya, Tanjore K. Suresh, David S. Walker, Sagar Borikar, Shrikant Vaidya
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Patent number: 10884960Abstract: In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.Type: GrantFiled: April 19, 2019Date of Patent: January 5, 2021Assignee: Cisco Technology, Inc.Inventors: Tanjore K. Suresh, David S. Walker, Ravi Shankar Palagummi, RaviKiran Kaidala Lakshman, Kar Wai Kam
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Publication number: 20200334184Abstract: In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.Type: ApplicationFiled: April 19, 2019Publication date: October 22, 2020Inventors: Tanjore K. Suresh, David S. Walker, Ravi Shankar Palagummi, RaviKiran Kaidala Lakshman, Kar Wai Kam
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Publication number: 20200320017Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.Type: ApplicationFiled: April 4, 2019Publication date: October 8, 2020Inventors: Ravikiran Kaidala Lakshman, Tanjore K. Suresh, Deepak Srinivas Mayya, Sagar Borikar
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Publication number: 20200278935Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman
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Publication number: 20200274829Abstract: The disclosed technology relates to a process for general-purpose ring buffer handling in a network controller. Specifically, general purpose ring buffers are used in software queue on both the host domain and the network controller to carry out user-defined protocols. The protocols define the relationship of the ring buffers in the host domain and the network controller domain (e.g. how data is moved and processed). The protocols minimize interruptions to the network controller. Furthermore, the implementation of ring buffers in the network controller domain also provides additional resources to the host domain for carrying out the user-defined protocols.Type: ApplicationFiled: February 25, 2019Publication date: August 27, 2020Inventors: Tanjore K Suresh, Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya
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Publication number: 20200097212Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Inventors: Ravikiran Kaidala Lakshman, Deepak Srinivas Mayya, Tanjore K. Suresh, David S. Walker, Sagar Borikar, Shrikant Vaidya