Patents by Inventor Ravikiran Rajagopal
Ravikiran Rajagopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9413578Abstract: An auxiliary reduced power analog-to-digital converter (ADC) is provided for use during sleep periods of a receiver. The auxiliary ADC has a reduced dynamic range but sufficient accuracy to allow demodulation of signaling information contained in an input signal and to update control parameters used for synchronization and channel estimation. As such, a main higher power, higher dynamic range ADC can be turned off during sleep periods, reducing receiver power consumption. The main ADC is turned on at the end of a sleep period, and the receiver can be ready for receiving data immediately using the main ADC because the control parameters are maintained up to date during the sleep period using the auxiliary ADC.Type: GrantFiled: April 7, 2015Date of Patent: August 9, 2016Assignee: Broadcom CorporationInventors: Ravikiran Rajagopal, Jeffrey Scott Putnam, Ramon Gomez
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Publication number: 20150327174Abstract: An auxiliary reduced power analog-to-digital converter (ADC) is, provided for use during sleep periods of a receiver. The auxiliary ADC has a reduced dynamic range but sufficient accuracy to allow demodulation of signaling information contained in an input signal and to update control parameters used for synchronization and channel estimation. As such, a main higher power, higher dynamic range ADC can be turned off during sleep periods, reducing receiver power consumption. The main ADC is turned on at the end of a sleep period, and the receiver can be ready for receiving data immediately using the main ADC because the control parameters are maintained up to date during the sleep period using the auxiliary ADC.Type: ApplicationFiled: April 7, 2015Publication date: November 12, 2015Applicant: Broadcom CorporationInventors: Ravikiran RAJAGOPAL, Jeffrey Scott Putnam, Ramon Gomez
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Patent number: 9008235Abstract: An auxiliary reduced power analog-to-digital converter (ADC) is provided for use during sleep periods of a receiver. The auxiliary ADC has a reduced dynamic range but sufficient accuracy to allow demodulation of signaling information contained in an input signal and to update control parameters used for synchronization and channel estimation. As such, a main higher power, higher dynamic range ADC can be turned off during sleep periods, reducing receiver power consumption. The main ADC is turned on at the end of a sleep period, and the receiver can be ready for receiving data immediately using the main ADC because the control parameters are maintained up to date during the sleep period using the auxiliary ADC.Type: GrantFiled: February 19, 2013Date of Patent: April 14, 2015Assignee: Broadcom CorporationInventors: Ravikiran Rajagopal, Jeffrey Scott Putnam, Ramon Gomez
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Publication number: 20140233679Abstract: An auxiliary reduced power analog-to-digital converter (ADC) is provided for use during sleep periods of a receiver. The auxiliary ADC has a reduced dynamic range but sufficient accuracy to allow demodulation of signaling information contained in an input signal and to update control parameters used for synchronization and channel estimation. As such, a main higher power, higher dynamic range ADC can be turned off during sleep periods, reducing receiver power consumption. The main ADC is turned on at the end of a sleep period, and the receiver can be ready for receiving data immediately using the main ADC because the control parameters are maintained up to date during the sleep period using the auxiliary ADC.Type: ApplicationFiled: February 19, 2013Publication date: August 21, 2014Applicant: Broadcom CorporationInventors: Ravikiran RAJAGOPAL, Jeffrey Scott PUTNAM, Ramon GOMEZ
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Patent number: 8644401Abstract: Provided is a method for performing channel estimation in an Orthogonal Frequency Division Multiplexed (OFDM) signal. The method includes performing the channel estimation based upon use of reserved tone channel carriers.Type: GrantFiled: November 20, 2009Date of Patent: February 4, 2014Assignee: Broadcom CorporationInventor: Ravikiran Rajagopal
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Patent number: 8625686Abstract: A window position optimization for a pilot-aided OFDM system is disclosed. A method of reducing aliasing in an orthogonal frequency division multiplexing (OFDM) system, using window optimization and pilots comprises receiving an RF signal including a pilot, generating a channel frequency response estimate, interpolating the channel estimate to calculate a pilot carrier frequency response, and dynamically selecting a window to capture a channel impulse response to prevent aliasing.Type: GrantFiled: July 18, 2008Date of Patent: January 7, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Yan Li, Feng Huang, Ravikiran Rajagopal, Troy Schaffer
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Patent number: 8625715Abstract: A method for performing channel estimation in an orthogonal frequency division multiplexing (OFDM) signal includes choosing reserved tones to be part of a pilot pattern, and using the reserved tones in the pilot pattern to perform the channel estimation. An apparatus for use in performing channel estimation in an OFDM system includes a receiver configured to receive a transmitted OFDM signal; a pilot symbol extractor configured to extract pilot symbols from the OFDM signal; and a channel estimator configured to perform the channel estimation, including using reserved tones as pilot tones.Type: GrantFiled: November 5, 2012Date of Patent: January 7, 2014Assignee: Advanced Micro Devices, Inc.Inventor: Ravikiran Rajagopal
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Patent number: 8306148Abstract: Provided is a method for performing channel estimation in an Orthogonal Frequency Division Multiplexed (OFDM) signal. The method includes performing the channel estimation based upon use of reserved tone channel carriers.Type: GrantFiled: March 31, 2009Date of Patent: November 6, 2012Assignee: Advanced Micro Devices, Inc.Inventor: Ravikiran Rajagopal
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Patent number: 8286057Abstract: A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encoding might refer to error detection in a packet frame at the data link layer, while a second logical dimension of coding might refer to error detection/correction encoding at a physical layer. For example, a data frame might be divided into several packets, each with a corresponding cyclic redundancy check (CRC) value as coding in the first logical dimension, which are then transmitted with a convolutional code as coding in the second logical dimension. The receiver performs iterative decoding in the first and second logical dimensions until either i) all errors are identified and corrected or ii) another type of stopping condition is met.Type: GrantFiled: April 20, 2009Date of Patent: October 9, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Azzedine Touzni, Ravikiran Rajagopal
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Patent number: 8265200Abstract: Provided is a method for synchronizing a multiple carrier receiver to receive a transmitted signal. The method includes determining a location of one or more scattered pilot carriers in a received symbol sequence and modulating the scattered pilot carriers in accordance with a single pseudorandom binary sequence. The method also includes performing phase error correction via the modulated scattered pilot carriers.Type: GrantFiled: August 24, 2009Date of Patent: September 11, 2012Assignee: Broadcom CorporationInventor: Ravikiran Rajagopal
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Patent number: 8139682Abstract: Methods and apparatus, including computer program products, are provided for channel estimation. In one aspect, there is provided a receiver including a demodulator for decoding a signal including at least one of a transmission parameter signaling (TPS) carrier and a data carrier. The receiver further includes a channel estimator, coupled to the demodulator, for determining a channel estimate for the TPS carrier. Moreover, the receiver includes an interpolator, coupled to the channel estimator, for determining, based on the determined channel estimate for the TPS carrier, another channel estimate for the data carrier. Related systems, methods, and articles of manufacture are also disclosed.Type: GrantFiled: December 20, 2007Date of Patent: March 20, 2012Assignee: Advanced Micro DevicesInventor: Ravikiran Rajagopal
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Publication number: 20100124300Abstract: Provided is a method for synchronizing a multiple carrier receiver to receive a transmitted signal. The method includes determining a location of one or more scattered pilot carriers in a received symbol sequence and modulating the scattered pilot carriers in accordance with a single pseudorandom binary sequence. The method also includes performing phase error correction via the modulated scattered pilot carriers.Type: ApplicationFiled: August 24, 2009Publication date: May 20, 2010Inventor: Ravikiran Rajagopal
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Publication number: 20100124293Abstract: Provided is a method for performing channel estimation in an Orthogonal Frequency Division Multiplexed (OFDM) signal. The method includes performing the channel estimation based upon use of reserved tone channel carriers.Type: ApplicationFiled: March 31, 2009Publication date: May 20, 2010Applicant: Advanced Micro Devices, Inc.Inventor: Ravikiran Rajagopal
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Publication number: 20100124296Abstract: Provided is a method for performing channel estimation in an Orthogonal Frequency Division Multiplexed (OFDM) signal. The method includes performing the channel estimation based upon use of reserved tone channel carriers.Type: ApplicationFiled: November 20, 2009Publication date: May 20, 2010Inventor: Ravikiran Rajagopal
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Publication number: 20100124292Abstract: Provided is a method for synchronizing a multiple carrier receiver to receive a transmitted signal. The method includes determining a location of one or more scattered pilot carriers in a received symbol sequence and modulating the scattered pilot carriers in accordance with a single pseudorandom binary sequence. The method also includes performing phase error correction via the modulated scattered pilot carriers.Type: ApplicationFiled: March 31, 2009Publication date: May 20, 2010Applicant: Advanced Micro Devices, Inc.Inventor: Ravikiran Rajagopal
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Publication number: 20100014600Abstract: A window position optimization for a pilot-aided OFDM system is disclosed. A method of reducing aliasing in an orthogonal frequency division multiplexing (OFDM) system, using window optimization and pilots comprises receiving an RF signal including a pilot, generating a channel frequency response estimate, interpolating the channel estimate to calculate a pilot carrier frequency response, and dynamically selecting a window to capture a channel impulse response to prevent aliasing.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yan Li, Feng Huang, Ravikiran Rajagopal, Troy Schaffer
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Publication number: 20090316841Abstract: A null detection and erasure decoding process for a frequency selective channel in a broadcasting system. An orthogonal frequency-division multiplexing (OFDM) receiver receives an input bitstream, determines a noise level of the received input bitstream, and then detects a null in the input bitstream based on the noise level. Once a null is detected, the presence of the null is signaled to a decoder, allowing the decoder to process the null as an erasure.Type: ApplicationFiled: June 20, 2008Publication date: December 24, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Yan Li, Feng Huang, Ravikiran Rajagopal, Troy Schaffer
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Publication number: 20090217138Abstract: A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encoding might refer to error detection in a packet frame at the data link layer, while a second logical dimension of coding might refer to error detection/correction encoding at a physical layer. For example, a data frame might be divided into several packets, each with a corresponding cyclic redundancy check (CRC) value as coding in the first logical dimension, which are then transmitted with a convolutional code as coding in the second logical dimension. The receiver performs iterative decoding in the first and second logical dimensions until either i) all errors are identified and corrected or ii) another type of stopping condition is met.Type: ApplicationFiled: April 20, 2009Publication date: August 27, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Azzedine Touzni, Ravikiran Rajagopal
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Publication number: 20090161773Abstract: Methods and apparatus, including computer program products, are provided for channel estimation. In one aspect, there is provided a receiver including a demodulator for decoding a signal including at least one of a transmission parameter signaling (TPS) carrier and a data carrier. The receiver further includes a channel estimator, coupled to the demodulator, for determining a channel estimate for the TPS carrier. Moreover, the receiver includes an interpolator, coupled to the channel estimator, for determining, based on the determined channel estimate for the TPS carrier, another channel estimate for the data carrier. Related systems, methods, and articles of manufacture are also disclosed.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: Advanced Micro Devices, Inc.Inventor: Ravikiran Rajagopal
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Patent number: 7530007Abstract: A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encoding might refer to error detection in a packet frame at the data link layer, while a second logical dimension of coding might refer to error detection/correction encoding at a physical layer. For example, a data frame might be divided into several packets, each with a corresponding cyclic redundancy check (CRC) value as coding in the first logical dimension, which are then transmitted with a convolutional code as coding in the second logical dimension. The receiver performs iterative decoding in the first and second logical dimensions until either i) all errors are identified and corrected or ii) another type of stopping condition is met.Type: GrantFiled: November 18, 2005Date of Patent: May 5, 2009Assignee: ATI Technologies Inc.Inventors: Azzedine Touzni, Ravikiran Rajagopal