Abstract: Various embodiments include systems, methods, and devices configured to reduce the amount of information communicated via system buses/fabrics when transferring data to and from one or more memories. A system master component may send a source address and a destination address to a direct memory access controller inside of, or adjacent to, a memory controller. The direct memory access controller and/or the memory controller may determine whether the source and destination addresses are inside relevant portions of the memory. When both the source and destination are inside the relevant portion of the memory, the memory controller may perform a memory-to-memory data transfer without accessing the system bus.

Abstract: Various embodiments include systems, methods, and devices configured to reduce the amount of information communicated via system buses/fabrics when transferring data to and from one or more memories. A system master component may send a source address and a destination address to a direct memory access controller inside of, or adjacent to, a memory controller. The direct memory access controller and/or the memory controller may determine whether the source and destination addresses are inside relevant portions of the memory. When both the source and destination are inside the relevant portion of the memory, the memory controller may perform a memory-to-memory data transfer without accessing the system bus.

Abstract: A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. information contained in the signal is selectively routed from the first port to a data recovery circuit.

Abstract: A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. information contained in the signal is selectively routed from the first port to a data recovery circuit.

Abstract: A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. Information contained in the signal is selectively routed from the first port to a data recovery circuit.

Abstract: A system wherein a signal over a Universal Serial Bus (USB) interface is received by a receiver component. A mixed signal block utilizes a mixed signal interface to transmit the signal to a processor block.

Abstract: A system wherein a signal over a Universal Serial Bus (USB) interface is received by a receiver component. A mixed signal block utilizes a mixed signal interface to transmit the signal to a processor block.

Abstract: The device and method that receives a signal from a first interface operating at a data rate. An extraction component extracts information from the signal to produce an information signal having a frequency distinct from the data rate of the first interface. A first receive clock component receives a first clock signal that has a frequency equal to a frequency of a second interface. A synchronizer component synchronizes the information signal through utilization of the first clock signal to the frequency of the second interface.

Abstract: A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. Information contained in the signal is selectively routed from the first port to a data recovery circuit.

Abstract: A data processing system having a device for processing data bits in parallel to generate bit-stuffed data, bit-unstuffed data, Non-Return-to-Zero-Inverted (NRZI) encoded data or NRZI-decoded data. The data processing system has a system clock operating at a system clock rate S. The device includes a data processing device and a local clock operating at a local clock rate L. The data processing device has a data storage element and a processing circuit and operates at the local clock rate L. The data storage element receives a number of bits N, where N is defined by the relation N=S/L. The processing circuit also generates N processed data bits.

Abstract: A data processing system having a device for processing data bits in parallel to generate bit-stuffed data, bit-unstuffed data, Non-Return-to-Zero-Inverted (NRZI) encoded data or NRZI-decoded data. The data processing system has a system clock operating at a system clock rate S. The device includes a data processing device and a local clock operating at a local clock rate L. The data processing device has a data storage element and a processing circuit and operates at the local clock rate L. The data storage element receives a number of bits N, where N is defined by the relation N=S/L. The processing circuit also generates N processed data bits.

Abstract: The device and method that receives a signal from a first interface operating at a data rate. An extraction component extracts information from the signal to produce an information signal having a frequency distinct from the data rate of the first interface. A first receive clock component receives a first clock signal that has a frequency equal to a frequency of a second interface. A synchronizer component synchronizes the information signal through utilization of the first clock signal to the frequency of the second interface.